MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 328

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

DBB—Delta Break B
RxRDYB—Channel B Receiver Ready or FIFO Full
TxRDYB—Channel B Transmitter Ready
XTAL_RDY—Serial Clock Running
DBA—Delta Break A
MOTOROLA
The function of this bit is programmed by MR1B bit 6.
This bit is the duplication of the TxRDY bit in SRB.
This bit is always read as a zero when the X1 clock is running. This bit cannot be
enabled to generate an interrupt.
1 = The channel B receiver has detected the beginning or end of a received break.
0 = The CPU32 has issued a channel B reset break-change interrupt command.
1 = If programmed as receiver ready, a character has been received in channel B
0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After
1 = The transmitter holding register is empty and ready to be loaded with a character.
0 = The transmitter holding register was loaded by the CPU32, or the transmitter is
1 = This bit is set at reset.
0 = This bit is cleared after the baud rate generator is stable. The CSR should not be
1 = The channel A receiver has detected the beginning or end of a received break.
0 = The CPU32 has issued a channel A reset break-change interrupt command.
Refer to 7.4.1.7 Command Register (CR) for more information on the reset
break-change interrupt command.
and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a
character has been transferred from the receiver shift register to the FIFO, and
the transfer has caused the channel B FIFO to become full (all three positions
are occupied).
this read, if more characters are still in the FIFO, the bit is set again after the
FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver
buffer. If a character is waiting in the receiver shift register because the FIFO is
full, the bit will be set again when the waiting character is loaded into the FIFO.
This bit is set when the character is transferred to the transmitter shift register.
This bit is also set when the transmitter is first enabled. Characters loaded into
the transmitter holding register while the transmitter is disabled are not
transmitted.
disabled.
accessed until this bit is zero.
Refer to 7.4.1.7 Command Register (CR) for more information on the reset
break-change interrupt command.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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