EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 99

• Manufacturer Part Number: EZ80190AZ050EC
• Description: IC WEBSERVER 50MHZ XTEMP 100lQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EC

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3123

SPI Registers
PS006614-1208
SPI Control Register
Table 39. SPI Control Register
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
IRQ_EN
6
5
SPI_EN
4
MASTER_EN
3
CPOL
2
CPHA
[1:0]
There are four registers in the Serial Peripheral Interface which provide control, status,
and data storage functions. These registers are called the SPI Control register (SPIx_CTL),
SPI Status register (SPIx_SR), SPI Receive Buffer register (SPIx_RBR), and SPI Transmit
Shift register (SPIx_TSR), where the x in each register name is either 0 or 1 depending on
which UZI device the SPI is located within. The SPI registers are described in this section.
The SPI Control Register, listed in
eral interface.
Value Description
0
1
0
0
1
0
1
0
1
0
1
00b
R/W
The SPI system interrupt is disabled.
The SPI system interrupt is enabled.
Reserved—must be 0.
The SPI is disabled.
The SPI is enabled.
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
The master SCK pin idles in a Low (0) state.
The master SCK pin idles in a High (1) state.
SS must go High after a transfer of every byte of data.
SS can remain Low to transfer any number of data bytes.
Reserved—must be 0.
7
0
R
6
0
R/W
Table
5
0
(SPI0_CTL = B6h, SPI1_CTL = BAh)
39, is used to control and set up the serial periph-
R/W
4
0
R/W
3
0
R/W
2
1
Product Specification
Serial Peripheral Interface
R
1
0
R
0
0
eZ80190
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