EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 18
![IC WEBSERVER 50MHZ XTEMP 100lQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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Manufacturer
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Price
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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
PS006614-1208
Pin
No.
23
24
25
26
27
28
29
Symbol
ADDR11 Address Bus
ADDR12 Address Bus
ADDR13 Address Bus
ADDR14 Address Bus
ADDR15 Address Bus
V
GND
DD
Function
Power Supply
Ground
Signal Direction
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Description
The ADDR11 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR12 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR13 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR14 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR15 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
Power Supply
Ground
Product Specification
Architectural Overview
8
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