EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 104
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 104 of 221
- Download datasheet (4Mb)
PS006614-1208
SDA Signal
SCL Signal
Acknowledge
Start Condition
I
can hold the SCL line Low to force the transmitter into a WAIT state. Data transfer then
continues when the receiver is ready for another byte of data and releases SCL.
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gener-
ated by the master. The transmitter releases the SDA line (High) during the ACK clock
pulse. The receiver must pull down the SDA line during the ACK clock pulse so that it
remains Low during the High period of this clock pulse. See
A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave receiver does not acknowledge the slave address (that is, the slave receiver
is unable to receive because it is performing some real-time function), the data line must
be left High by the slave. The master then generates a STOP condition to abort the trans-
fer.
If a slave receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the STOP condition.
If a master receiver is involved in a transfer, it must signal the end of the data transfer to
the slave transmitter by not generating an ACK on the final byte clocked out of the slave.
The slave transmitter must release the data line to allow the master to generate a STOP or
a repeated START condition.
2
C Acknowledge (ACK). Data is transferred with the msb first, see
S
MSB
1
2
Figure 18. I
Acknowledge
From Receiver
8
9
2
C Frame Structure
Clock Line Held Low By Receiver
1
Acknowledge
From Receiver
Figure 19
ACK
9
Product Specification
Figure
I2C Serial I/O Interface
on page 95.
Stop Condition
18. A receiver
P
94
Related parts for EZ80190AZ050EC
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Communication Controllers, ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP)
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
KIT DEV FOR Z8 ENCORE 16K TO 64K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
KIT DEV Z8 ENCORE XP 28-PIN
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
DEV KIT FOR Z8 ENCORE 8K/4K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
KIT DEV Z8 ENCORE XP 28-PIN
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
DEV KIT FOR Z8 ENCORE 4K TO 8K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
CMOS Z8 microcontroller. ROM 16 Kbytes, RAM 256 bytes, speed 16 MHz, 32 lines I/O, 3.0V to 5.5V
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Low-cost microcontroller. 512 bytes ROM, 61 bytes RAM, 8 MHz
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Z8 4K OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
CMOS SUPER8 ROMLESS MCU
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
SL1866 CMOSZ8 OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
SL1866 CMOSZ8 OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
OTP (KB) = 1, RAM = 125, Speed = 12, I/O = 14, 8-bit Timers = 2, Comm Interfaces Other Features = Por, LV Protect, Voltage = 4.5-5.5V
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Zilog, Inc.
Datasheet: