EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 166
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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PS006614-1208
Table 83. ZDI Address Match Registers
ZDI Break Control Register
Table 84. ZDI Break Control Register (ZDI_BRK_CTL = 10h in the ZDI Write Only Register
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Bit
Position
[7:0]
ZDI_ADDRX_L,
ZDI_ADDRX_H,
or
ZDI_ADDRX_U
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
BRK_NEXT
ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h, ZDI_ADDR2_U = 0Ah, ZDI_ADDR3_L = 0Ch,
ZDI_ADDR0_U = 02h, ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h, ZDI_ADDR1_U = 06h,
The ZDI Break Control register,
Value Description
0
1
Value Description
00h–
FFh
ZDI_ADDR3_H = 0Dh, ZDI_ADDR3_U = 0Eh)
The ZDI break on the next CPU instruction is disabled.
The ZDI break on the next CPU instruction is enabled. The
CPU is instructed to use multiple Op Codes and multiple byte
operands. This function only breaks on the first Op Code in a
multiple Op Code instruction. If both the ZCL and ZDA pins are
forced Low (0) during a RESET, this bit is set to 1 and a break
occurs on the first instruction following the RESET.
W
W
X
7
7
0
The four sets of ZDI address match registers are used for
setting the addresses for generating break points. The
24-bit addresses are returned by {ZDI_ADDRx_U,
ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
W
W
X
6
6
0
Address Space)
Table
W
W
X
5
5
0
(ZDI_ADDR0_L = 00h, ZDI_ADDR0_H = 01h,
84, is used to enable break points.
W
W
X
4
4
0
W
W
X
3
3
0
W
W
X
2
2
0
Product Specification
W
W
X
1
1
0
Zilog Debug Interface
W
W
X
0
0
0
eZ80190
156
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