EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 19

• Manufacturer Part Number: EZ80190AZ050EC
• Description: IC WEBSERVER 50MHZ XTEMP 100lQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EC

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3123

Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
PS006614-1208
Pin
No.
30
31
32
33
34
Symbol
ADDR16 Address Bus
ADDR17 Address Bus
ADDR18 Address Bus
ADDR19 Address Bus
ADDR20 Address Bus
Function
Signal Direction
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Description
The ADDR16 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR17 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR18 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR19 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR20 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
Product Specification
Architectural Overview
9