EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 47
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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PS006614-1208
Note:
Note:
Table 7. Timer Data High Byte Registers
Timer Reload Low Byte Registers
Table 8. Timer Reload Low Byte Registers
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
TMR_DR_H
Bit
Reset
CPU Access
Note: W = Write Only.
Data High Byte register. The Timer Data High Byte register value is latched when a read
of the Timer Data Low Byte register occurs.
The timer data registers and timer reload registers share the same address space.
The Timer Reload Low Byte registers, listed in
(MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is
reloaded into the timer upon end-of-count. When the RST_EN bit (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
The timer data registers and timer reload registers share the same address space.
TMR2_DR_H = 0088h, TMR3_DR_H = 008Bh, TMR4_DR_H = 008Eh)
TMR2_RR_L = 0087h, TMR3_RR_L = 008Ah, TMR4_RR_L = 008Dh)
Value
00h–FFh These bits represent the High byte of the 2-byte timer data
W
R
7
0
7
0
Description
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 15
most-significant bit (msb) of the 16-bit timer data value. Bit
0 is bit 8 of the 16-bit timer data value.
W
R
6
0
6
0
W
R
5
0
5
0
(TMR0_DR_H = 0082h, TMR1_DR_H = 0085h,
(TMR0_RR_L = 0081h, TMR1_RR_L = 0084h,
W
R
4
0
4
0
Table
W
R
3
0
3
0
8, stores the most significant byte
W
R
2
0
2
0
Programmable Reload Timers
Product Specification
W
R
1
0
1
0
W
R
0
0
0
0
eZ80190
37
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