EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 67

IC WEBSERVER 50MHZ XTEMP 100lQFP

EZ80190AZ050EC

Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80190AZ050EC

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123

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Manufacturer
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Price
Part Number:
EZ80190AZ050EC
Manufacturer:
Zilog
Quantity:
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EZ80190AZ050EC00TR
Manufacturer:
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Quantity:
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PS006614-1208
Chip Select x Control Register
Table 20. Chip Select x Control Register
Bit
Position
[7:0]
CS_UBR
Bit
CS 0 Reset
CS 1 Reset
CS 2 Reset
CS 3 Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:5]
CS_WAIT
4
CS_IO
The Chip Select x Control register, listed in
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is
registers is
Value Description
00h–
FFh
Value Description
000
001
010
011
100
101
110
111
0
1
00h
.
This bit specifies the upper bound of the Chip Select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining if a Chip Select signal should be generated.
R/W
0 WAIT states are inserted when this Chip Select is active.
1 WAIT state is inserted when this Chip Select is active.
2 WAIT states are inserted when this Chip Select is active.
3 WAIT states are inserted when this Chip Select is active.
4 WAIT states are inserted when this Chip Select is active.
5 WAIT states are inserted when this Chip Select is active.
6 WAIT states are inserted when this Chip Select is active.
7 WAIT states are inserted when this Chip Select is active.
An address match results in a Memory Chip Select.
An address match results in an I/O Chip Select.
7
1
0
0
0
R/W
E8h
6
1
0
0
0
B0h, CS3_CTL = B3h)
, while the reset state for the 3 other Chip Select control
R/W
5
1
0
0
0
(CS0_CTL = AAh, CS1_CTL = ADh, CS2_CTL =
R/W
Table
4
0
0
0
0
20, enables the Chip Selects, specifies
R/W
3
1
0
0
0
R/W
2
0
0
0
0
Chip Selects and Wait States
Product Specification
R/W
1
0
0
0
0
R/W
0
0
0
0
0
eZ80190
57

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