EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 94
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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Serial Peripheral Interface
SPI Signals
PS006614-1208
Baud Rate
Generator
Master In Slave Out
Bit 7
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented
communication channel that employs a four-wire interface. The SPI block consists of a
transmitter, receiver, clock generator, and control unit. During an SPI transfer, data is sent
and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The
eZ80190 device contains two SPI devices—one within each Universal Zilog Interface
(UZI) block. The SPI devices may be configured as either master or slave. The connection
of two SPI devices (one master and one slave) and the direction of data transfer is dis-
played in
The four basic SPI signals (MISO, MOSI, SS, and SCK) are discussed in the following
paragraphs. Each signal is described in both MASTER and SLAVE modes.
The Master In Slave Out (MISO) pin is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data, with the msb
sent first. The MISO pin of a slave device is placed in a high-impedance state if the slave
8-bit Shift Register
Master
Figure
13.
Bit 0
Figure 13. SPI Master
MISO
MOSI
SCK
MISO
MOSI
SCK
—Slave Connection
Bit 7
8-bit Shift Register
Slave
Product Specification
Serial Peripheral Interface
Bit 0
eZ80190
84
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