EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 119
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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PS006614-1208
Table 53. I
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:3]
STAT
[2:0]
There are 29 possible status codes, listed in
the status code
and the IFLG bit in the I2Cx_CTL register is not set. All other status codes correspond to
a defined state of the I
When the device enters each of these states, the corresponding status code appears in this
register and the IFLG bit in the I2Cx_CTL register is set. When the IFLG bit is cleared,
the status code returns to
Table 54. I
Code
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
2
C Status Registers
000
Value
00000–
11111
2
Status
Bus error
START condition transmitted
Repeated START condition transmitted
Address + write bit transmitted, ACK received
Address + write bit transmitted, ACK not received
Data byte transmitted in MASTER mode, ACK received
Data byte transmitted in MASTER mode, ACK not received
Arbitration lost in address or data byte
Address + read bit transmitted, ACK received
Address + read bit transmitted, ACK not received
Data byte received in MASTER mode, ACK transmitted
Data byte received in MASTER mode, NACK transmitted
Slave address + write bit received, ACK transmitted
C Status Codes
F8h
, no relevant status information is available, no interrupt is generated
Description
5-bit I
Reserved.
R
1
2
C.
2
F8h
C status code.
R
1
.
(I2C0_SR = CCh, I2C1_SR = DCh) (Continued)
R
1
Table
R
1
54. When the I2Cx_SR register contains
R
1
R
0
Product Specification
R
0
I2C Serial I/O Interface
R
0
109
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