MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 66

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
15 Clocking
This section describes the PLL configuration of the MPC8555E. Note that the platform clock is identical
to the CCB clock.
15.1
Table 44
specifications for the memory bus.
e500 core
processor
frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3. 1000 MHz frequency supports only a 1.3 V core.
66
Characteristic
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the clocking specifications for the processor core and
Clock Ranges
Memory bus frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3. 1000 MHz frequency supports only a 1.3 V core.
the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to
Ratio,” and
Min
400
533 MHz
Section 15.2, “Platform/System PLL
Characteristic
Section 15.3, “e500 Core PLL
Max
533
Table 44. Processor Core Clocking Specifications
Table 45. Memory Bus Clocking Specifications
Min
400
600 MHz
Maximum Processor Core Frequency
Max
600
Ratio,” for ratio settings.
Min
400
533, 600, 667, 883, 1000 MHz
Maximum Processor Core
667 MHz
Ratio,” and
Min
100
Max
667
Frequency
Section 15.3, “e500 Core PLL
Min
400
833 MHz
Section 15.2, “Platform/System PLL
Max
166
Max
833
Table 44
Unit
MHz
Min
400
1000 MHz
provides the clocking
Freescale Semiconductor
Ratio,” for ratio settings.
1000
Max
Notes
1, 2, 3
MHz 1, 2, 3
Unit Notes