MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 16

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RESET Initialization
4.3
Table 8
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8555E.
Table 10
16
RTC clock high time
RTC clock low time
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
Input hold time for POR configs (including PLL config) with
respect to negation of HRESET
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
Notes:
1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8555E. See the MPC8555E
minimum and an 8:1 ratio results in the maximum.
PowerQUICC™ III Integrated Communications Processor Reference Manual for more details.
RESET Initialization
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the real time clock (RTC) AC timing specifications.
provides the PLL and DLL lock times.
Real Time Clock Timing
Parameter/Condition
Table 9
Parameter/Condition
Parameter/Condition
provides the RESET initialization AC timing specifications.
Table 9. RESET Initialization Timing Specifications
Table 8. RTC AC Timing Specifications
Table 10. PLL and DLL Lock Times
Symbol
t
t
RTCH
RTCL
t
t
CCB_CLK
CCB_CLK
7680
Min
100
512
100
Min
Min
—
2 x
2 x
4
2
—
Typical
—
—
122,880
Max
Max
100
—
—
—
—
—
5
Max
—
—
CCB Clocks
Freescale Semiconductor
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Unit
Unit
μs
μs
μs
Unit
ns
ns
Notes
Notes
Notes
1, 2
—
—
—
—
1
—
1
1
1