MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 47

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 29
10.3
Freescale Semiconductor
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDA/SCL rise time
TDM Output Signals
Note:
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
PIO outputs
TDM Input Signals
PIO inputs
CPM I2C AC Specification
1.
2.
3.
4.
shows TDM input and output signals.
Sys clk
Input sampled on the rising edge and output driven on the rising edge (shown).
Input sampled on the rising edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the rising edge.
Characteristic
2
There are 4 possible TDM timing conditions:
2
Serial CLKIN
2
2
t
PIIVKH
Figure 29. TDM Signal AC Timing Diagram
t
TDIVKH
Figure 30. PIO Signal Diagram
Expression
t
t
t
t
t
t
Table 35. I2C Timing
t
t
t
SDHDL
SCLCH
SCHCL
SCHDL
SDVCH
SDLCL
SCLDX
PIIXKH
SRISE
f
f
SCL
SCL
t
TDIXKH
t
TDKHOX
BRGCLK/16512
2/(divider * f
3/(divider * f
2/(divider * f
3/(divider * f
1/(2.2 * f
1/(2.2 * f
1/(2.2 * f
Min
0
-
SCL
SCL
SCL
SCL
SCL
SCL
SCL
All Frequencies
t
)
)
)
PIKHOX
)
)
)
)
BRGCLK/48
1/(10 * f
F
MAX
Max
-
-
-
-
(2)
-
-
-
(1)
SCL
)
Unit
Hz
Hz
s
s
s
s
s
s
s
s
CPM
47