MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 51
MPC855TCVR50D4
Manufacturer Part Number
MPC855TCVR50D4
Description
IC MPU POWERQUICC 50MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC855TVR50D4.pdf
(15 pages)
2.MPC8555ECVTALF.pdf
(88 pages)
3.MPC855TCVR50D4.pdf
(80 pages)
Specifications of MPC855TCVR50D4
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC855TCVR50D4
Manufacturer:
FREESCAL
Quantity:
246
Company:
Part Number:
MPC855TCVR50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC855TCVR50D4R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 32
Figure 33
Figure 34
Figure 35
Freescale Semiconductor
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the AC test load for TDO and the boundary-scan outputs of the MPC8555E.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
provides the boundary-scan timing diagram.
External Clock
Data Outputs
Data Outputs
Data Inputs
External Clock
Boundary
Boundary
Boundary
TRST
JTAG
JTAG
Output
t
Output Data Valid
JTKLDX
Figure 32. AC Test Load for the JTAG Interface
Figure 33. JTAG Clock Input Timing Diagram
Figure 35. Boundary-Scan Timing Diagram
VM
t
JTKHKL
Figure 34. TRST Timing Diagram
VM
t
Z
VM
JTKLDZ
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
t
0
JTKLDV
t
= 50 Ω
JTG
VM
t
TRST
t
JTDVKH
VM
R
VM
Output Data Valid
L
Data Valid
= 50 Ω
Input
t
JTGR
VM
OV
DD
t
t
JTDXKH
JTGF
/2
JTAG
51