MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 2

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
1
The following section provides a high-level overview of the MPC8555E features.
major functional units within the MPC8555E.
1.1
The following lists an overview of the MPC8555E feature set.
2
•
MIIs/RMIIs
UTOPIA
Overview
Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
SDRAM
MPHY
TDMs
GPIO
IRQs
Key Features
32b
I/Os
DDR
DDR SDRAM Controller
Local Bus Controller
Interrupt Controller
Programmable
SCC/USB
I
2
C Controller
CPM
SMC
SMC
FCC
FCC
SCC
SCC
DUART
SPI
I
2
C
Generators
Parallel I/O
Baud Rate
I-Memory
Controller
Interrupt
DPRAM
Engine
Timers
Serial
RISC
CPM
ROM
DMA
Figure 1. MPC8555E Block Diagram
Coherency
Module
OCeaN
e500
Security
Engine
Core Complex
256-Kbyte
L2 Cache/
SRAM
Bus
64/32b PCI Controller
0/32b PCI Controller
10/100/1000 MAC
10/100/1000 MAC
DMA Controller
32-Kbyte L1
I Cache
Figure 1
e500 Core
Freescale Semiconductor
MII, GMII, TBI,
RTBI, RGMIIs
32-Kbyte L1
D Cache
shows the