ADE5569ASTZF62 Analog Devices Inc, ADE5569ASTZF62 Datasheet - Page 94

• Manufacturer Part Number: ADE5569ASTZF62
• Description: IC METER/8052/RTC/LCD DRV 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE5569ASTZF62

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (62kB)
• Controller Series: ADE55xx
• Ram Size: 2.25K x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADE5166/ADE5169/ADE5566/ADE5569
INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 85 and Table 86, respectively. Most of the
interrupts have flags associated with them.
Table 85. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
RI2 + TI2
TF2 + EXF2
ITEMP (Temperature ADC)
IPSM (Power Supply)
IADE (Energy Measurement DSP)
Table 86. Status Flags
Interrupt Source
ITEMP (Temperature ADC)
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
1
A functional block diagram of the interrupt system is shown in
Figure 89. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE5166/
ADE5169/ADE5566/ADE5569 from PSM2 mode, a pending
external interrupt is generated. When the EX0 bit (Bit 0) or the
EX1 bit (Bit 2) in the interrupt enable SFR (IE, Address 0xA8) is
set to enable external interrupts, the program counter is loaded
with the IE0 or IE1 interrupt vector. The IE0 and IE1 interrupt
flags (Bit 1 and Bit 3, respectively) in the Timer/Counter 0 and
Timer/Counter 1 control SFR (TCON, Address 0x88) are not
affected by events that occur when the 8052 MCU core is shut
down during PSM2 mode (see the Power Supply Management
(PSM) Interrupt section).
The temperature ADC and I
that pending interrupts cannot be cleared without entering their
respective interrupt service routines. Clearing the I
bits in the SPI interrupt status SFR (SPISTAT, Address 0xEA)
does not cancel a pending I
There is no specific flag for ISPI/I2CI; however, all flags for SPI2CSTAT need to be read to assess the reason for the interrupt.
2
C/SPI interrupt. These interrupts
2
C/SPI interrupts are latched such
Flag
N/A
SPI2CSTAT
SPI2CSTAT
TIMECON[6]
TIMECON[2]
WDCON[2]
Flag
TCON[1]
TCON[5]
TCON[3]
TCON[7]
SCON[1]
SCON[0]
SCON2[1]
SCON2[0]
T2CON[7]
T2CON[6]
N/A
IPSMF[6]
MIRQSTL[7]
1
Bit Name
IE0
TF0
IE1
TF1
TI
RI
TI2
RI2
TF2
EXF2
N/A
FPSM
ADEIRQFLAG
Bit Name
N/A
N/A
N/A
ALFLAG
ITFLAG
WDS
2
C/SPI status
Rev. C | Page 94 of 156
External Interrupt 0.
Timer 0.
External Interrupt 1.
Timer 1.
Transmit interrupt.
Receive interrupt.
Transmit 2 interrupt.
Receive 2 interrupt.
Timer 2 overflow flag.
Timer 2 external flag.
Description
Temperature ADC interrupt. Does not have an interrupt flag associated with it.
PSM interrupt flag.
Read MIRQSTH, MIRQSTM, MIRQSTL.
Description
Temperature ADC interrupt. Does not have a status flag associated with it.
SPI interrupt status register.
I
RTC alarm flag.
RTC interrupt flag.
Watchdog timeout flag.
2
C interrupt status register.
remain pending until the I
Their respective interrupt service routines are entered shortly
thereafter.
The RTC interrupts are driven by the alarm and interval flags.
Pending RTC interrupts can be cleared without entering the
interrupt service routine by clearing the corresponding RTC
flag in software. Entering the interrupt service routine alone
does not clear the RTC interrupt.
Figure 89 shows how the interrupts are cleared when the inter-
rupt service routines are entered. Some interrupts with multiple
interrupt sources are not automatically cleared, specifically, the
PSM, ADE, UART, UART2, and Timer 2 interrupt vectors. Note
that the INT0 and INT1 interrupts are cleared only if the external
interrupt is configured to be triggered by a falling edge by setting
IT0 (Bit 0) and IT1 (Bit 2) in the Timer/Counter 0 and Timer/
Counter 1 control SFR (TCON, Address 0x88). If INT0 or INT1
is configured to interrupt on a low level, the interrupt service
routine is reentered until the respective pin goes high.
2
C/SPI interrupt vectors are enabled.