ADE5569ASTZF62 Analog Devices Inc, ADE5569ASTZF62 Datasheet - Page 61
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ADE5569ASTZF62
Manufacturer Part Number
ADE5569ASTZF62
Description
IC METER/8052/RTC/LCD DRV 64LQFP
Manufacturer
Analog Devices Inc
Datasheet
1.ADE5569ASTZF62-RL.pdf
(156 pages)
Specifications of ADE5569ASTZF62
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (62kB)
Controller Series
ADE55xx
Ram Size
2.25K x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Ic Function
Single Phase Energy Measurement IC
Supply Voltage Range
3.13V To 3.46V, 2.4V To 3.7V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADE5569ASTZF62
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
ADE5569ASTZF62-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, active power
is defined as the rate of energy flow. This relationship can be
expressed mathematically, as shown in Equation 11.
where:
P is power.
E is energy.
Conversely, energy is given as the integral of power.
The ADE5166/ADE5169/ADE5566/ADE5569 achieve the inte-
gration of the active power signal by continuously accumulating
the active power signal in an internal, nonreadable, 49-bit energy
register. The WATTHR register (Address 0x01) represents the
upper 24 bits of this internal register. This discrete time
accumulation or summation is equivalent to integration in
continuous time. Equation 13 expresses the relationship.
where:
n is the discrete time sample number.
T is the discrete time sample period.
The discrete time sample period (T) for the accumulation
register in the ADE5166/ADE5169/ADE5566/ADE5569 is 1.22 μs
(5/MCLK). In addition to calculating the energy, this integration
removes any sinusoidal components that may be in the active
power signal. Figure 66 shows this discrete time integration or
E
E
P =
=
=
∫
∫
dE
dt
P
P
) (
) (
t
t
CHANNEL
CURRENT
CHANNEL
VOLTAGE
dt
dt
=
lim
t
→
0
⎧
⎨
⎩
n
∑
∞
=
1
P
T
(
nT
)
×
ACTIVE POWER
T
LPF2
MCLK
sgn
⎫
⎬
⎭
SIGNAL
5
TIME (nT)
WATTOS[15:0]
2
6
2
+
5
+
WAVEFORM
2
REGISTER
–6
VALUES
2
–7
Figure 66. Active Energy Calculation
2
–8
FOR WAVEFORM
SAMPLING
WGAIN[11:0]
Rev. C | Page 61 of 156
(11)
(12)
(13)
WDIV[7:0]
%
accumulation. The active power signal in the waveform register
is continuously added to the internal active energy register.
The active energy accumulation depends on the setting of
POAM (Bit 1) and ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F). When both bits are cleared, the addition is signed
and, therefore, negative energy is subtracted from the active
energy contents. When both bits are set, the ADE5166/ADE5169/
ADE5566/ADE5569 are set to the more restrictive mode, the
positive-only accumulation mode.
When POAM (Bit 1) in the ACCMODE register (Address 0x0F)
is set, only positive power contributes to the active energy accumu-
lation. When ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F) is set, the absolute active power is used for the
active energy accumulation (see the Watt Absolute Accumulation
Mode section).
The output of the multiplier is divided by the value in the WDIV
register (Address 0x24). If the value in the WDIV register is equal
to 0, the internal active energy register is divided by 1. WDIV is an
8-bit, unsigned register. After dividing by WDIV, the active energy
is accumulated in a 49-bit internal energy accumulation register.
The upper 24 bits of this register are accessible through a read
to the active energy register (WATTHR, Address 0x01[23:0]).
A read to the RWATTHR register (Address 0x02) returns the
contents of the WATTHR register, and the upper 24 bits of the
internal register are cleared. As shown in Figure 66, the active
power signal is accumulated in an internal 49-bit, signed register.
The active power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting
the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
TO
DIGITAL-TO-FREQUENCY
CONVERTER
+
+
ADE5166/ADE5169/ADE5566/ADE5569
48
23
WATTHR[23:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
0
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
WATTHR[23:0] REGISTER
0