ADE5569ASTZF62 Analog Devices Inc, ADE5569ASTZF62 Datasheet - Page 80

• Manufacturer Part Number: ADE5569ASTZF62
• Description: IC METER/8052/RTC/LCD DRV 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE5569ASTZF62

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (62kB)
• Controller Series: ADE55xx
• Ram Size: 2.25K x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADE5166/ADE5169/ADE5566/ADE5569
Table 59. Program Control SFR (PCON, Address 0x87)
Bit
7
[6:0]
Table 60. Data Pointer Low SFR (DPL, Address 0x82)
Bit
[7:0]
Table 61. Data Pointer High SFR (DPH, Address 0x83)
Bit
[7:0]
Table 62. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83)
Bit
[15:0]
Table 63. Stack Pointer SFR (SP, Address 0x81)
Bit
[7:0]
Table 64. Stack Pointer High SFR (SPH, Address 0xB7)
Bit
7
6
5
4
3
2
1
0
Table 65. Stack Boundary SFR (STCON, Address 0xBF)
Bit
[7:3]
2
1
0
Table 66. Configuration SFR (CFG, Address 0xAF)
Bit
7
6
5
Mnemonic
SMOD
Reserved
Mnemonic
DPL
Mnemonic
DPH
Mnemonic
DP
Mnemonic
SP
Mnemonic
Reserved
SBFLG
SSA[10]
SSA[9]
SSA[8]
SP[10]
SP[9]
SP[8]
Mnemonic
WTRLINE
INT_RST
SBE
WTRLFG
Mnemonic
Reserved
EXTEN
SCPS
Default
0
0
Default
0
Default
0
Default
0
Default
0
Default
1
0
0
0
1
0
0
1
Default
0
0
0
0
Default
1
0
0
Description
Double baud rate control.
Reserved. These bits must be kept at 0 for proper operation.
Description
These bits contain the low byte of the data pointer.
Description
These bits contain the high byte of the data pointer.
Description
These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL SFRs.
Description
These bits contain the eight LSBs of the pointer for the stack.
Description
Reserved. This bit must be set to 1 for proper operation.
Stack bottom flag.
Stack Starting Address Bit 10.
Stack Starting Address Bit 9.
Stack Starting Address Bit 8.
Stack Address Bit 10.
Stack Address Bit 9.
Stack Address Bit 8.
Description
Contains the stack waterline setting bits.
Interrupt/reset selection bit.
INT_RST
0
1
Stack boundary enable bit.
Waterline flag.
Description
Reserved. This bit should be left set for proper operation.
Enhanced UART enable bit.
EXTEN
0
1
Synchronous communication selection bit.
SCPS
0
1
Result
An interrupt is issued when a stack violation occurs
A reset is issued when a stack violation occurs
Result
Standard 8052 UART without enhanced error checking features
Enhanced UART with enhanced error checking (see the UART Additional Features section)
Result
I
SPI port is selected for control of the shared I
2
C port is selected for control of the shared I
Rev. C | Page 80 of 156
2
2
C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs
C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs