ADE5569ASTZF62 Analog Devices Inc, ADE5569ASTZF62 Datasheet - Page 71

• Manufacturer Part Number: ADE5569ASTZF62
• Description: IC METER/8052/RTC/LCD DRV 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE5569ASTZF62

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (62kB)
• Controller Series: ADE55xx
• Ram Size: 2.25K x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Line Cycle Apparent Energy Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are designed with
a special apparent energy accumulation mode that simplifies the
calibration process. By using the on-chip, zero-crossing detection,
the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the
apparent power signal in the LVAHR register (Address 0x09) for
an integral number of half cycles, as shown in Figure 78. The line
cycle apparent energy accumulation mode is always active.
The number of half-line cycles is specified in the LINCYC
register (Address 0x12), which is an unsigned 16-bit register.
The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate
apparent power for up to 65,535 combined half cycles. Because
the apparent power is integrated on the same integral number
of line cycles as the line active register and reactive energy register,
these values can easily be compared. The energies are calculated
more accurately because of this precise timing control and provide
all the information needed for reactive power and power factor
calculation.
At the end of an energy calibration cycle, the CYCEND flag (Bit 2)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.
If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) is set, the 8052 core has a pending
ADE interrupt.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVAHR register (Address 0x09) is reset and a
new accumulation starts at the next zero crossing. The number of
half-line cycles is then counted until LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line apparent energy accumulation uses the same signal path as
the apparent energy accumulation. The LSB size of these two
registers is equivalent.
VOLTAGE CHANNEL
FROM
ADC
LPF1
APPARENT POWER
ZERO-CROSSING
DETECTION
Figure 78. Line Cycle Apparent Energy Accumulation Mode
OR I
rms
VADIV[7:0]
%
Rev. C | Page 71 of 156
LINCYC[15:0]
CALIBRATION
CONTROL
+
+
Apparent Power No Load Detection
The ADE5166/ADE5169/ADE5566/ADE5569 include a no load
threshold feature on the apparent power that eliminates any creep
effects in the meter. The ADE5166/ADE5169/ADE5566/ADE5569
accomplish this by not accumulating energy if the multiplier output
is below the no load threshold. When the apparent power is
below the no load threshold, the VANOLOAD flag (Bit 2) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
If the VANOLOAD bit (Bit 2) is set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
VANOLOAD status bit is cleared (see the Energy Measurement
Interrupts section).
The no load threshold level can be selected by setting the
VANOLOAD bits (Bits[5:4]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.030%, 0.015%, and 0.0075% of the
full-scale output frequency of the multiplier, respectively.
This no load threshold can also be applied to the I
output when selected. In this case, the level of the no load
threshold is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy
meter, the ADE5166/ADE5169/ADE5566/ADE5569 are capable
of accumulating the ampere-hours instead of apparent power into
the VAHR (Address 0x07), RVAHR (Address 0x08), and LVAHR
(Address 0x09) registers. When VARMSCFCON (Bit 3) of the
MODE2 register (Address 0x0C) is set, the VAHR, RVAHR,
and LVAHR registers and the input for the digital-to-frequency
converter accumulate I
processing and calibration registers available for apparent power
and energy accumulation remain the same when ampere-hour
accumulation is selected. However, the scaling difference between
I
bration in the VAGAIN (Address 0x1F), VADIV (Address 0x26),
CFxNUM (Address 0x27 and Address 0x29), and CFxDEN
(Address 0x28 and Address 0x2A) registers.
rms
and apparent power requires independent values for gain cali-
ADE5166/ADE5169/ADE5566/ADE5569
48
23
LVAHR[23:0]
0
rms
instead of apparent power. All the signal
LVAHR REGISTER IS
UPDATED EVERY LINCYC
ZERO CROSSING WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
0
rms
pulse