CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 59

• Manufacturer Part Number: CY8CTMG200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2954

6.2
The following registers are associated with the General Purpose I/O (GPIO) and are listed in address order. The register
descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed
out are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of 0.
For a complete table of General Purpose I/O registers, refer to the
For a selected GPIO block, the individual registers are addressed in the
names, the ‘x’ is the port number, configured at the PSoC device level (x = 0 to 4 typically). All register values are readable,
except for the PRTxDR register; reads of this register return the pin state instead of the register bit state.
6.2.1
The Port Data Register (PRTxDR) allows for write or read
access of the current logical equivalent of the voltage on the
pin.
Bits 7 to 0: Data[7:0]. Writing the PRTxDR register bits set
the output drive state for the pin to high (for Data = 1) or low
(Data = 0), unless a bypass mode is selected (see
Bypass on page
6.2.2
The Port Interrupt Enables (PRTxIE) registers enable or dis-
able interrupts from individual GIPIO pins.
Bits 7 to 0: InterruptEnables[7:0]. These bits enable the
corresponding port pin interrupt. Only four LSB pins are
used since this port has four pins.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,xxh
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
0,xxh
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
Address
Address
refer to the
refer to the
Register Definitions
PRTxDR
PRTxIE
Core Register Summary on page
Core Register Summary on page
PRTxDR Registers
PRTxIE Registers
Name
Name
58).
Bit 7
Bit 7
Bit 6
Bit 6
24.
24.
Bit 5
Bit 5
Data
InterruptEnables[7:0]
Bit 4
Bit 4
Data[7:0]
Reading the PRTxDR register returns the actual pin state,
as seen by the input buffer. This may not be the same as the
expected output state, if the load pulls the pin more strongly
than the pin’s configured output drive. See
page 56
For additional information, refer to the
page
‘0’ is port pin interrupt disabled for the corresponding pin.
‘1’ is port pin interrupt enabled for the corresponding pin.
Interrupt mode is determined by the IOINT bit in the
IO_CFG1
For additional information, refer to the
page
Core Register Summary on page
188.
188.
Bit 3
Bit 3
Core Register Summary on page
for a detailed discussion of digital I/O.
register.
Bit 2
Bit 2
Bit 1
Bit 1
General Purpose I/O (GPIO)
24.
PRTxDR register on
PRTxDR register on
Bit 0
Bit 0
24. In the register
Digital I/O on
RW : 00
RW : 00
Access
Access
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