CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 258

• Manufacturer Part Number: CY8CTMG200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2954

CPU_SCR0
21.3.66 CPU_SCR0
This register is used to convey the status and control of events for various functions of a PSoC device.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 137
Bit
7
5
4
3
0
258
Individual Register Names and Addresses:
CPU_SCR0 : x,FFh
Access : POR
Bit Name
x,FFh
GIES
WDRS
PORS
Sleep
STOP
Name
in the System Resets chapter.
System Status and Control Register 0
GIES
R : 0
7
6
Description
Global Interrupt Enable Status. It is recommended that the user read the Global Interrupt Enable Flag
bit from the
Flag register is now readable at address x,F7h (read only).
Watchdog Reset Status. This bit may not be set by user code; however, it may be cleared by writing
a ’0’.
0
1
Power On Reset Status. This bit may not be set by user code; however, it may be cleared by writing a
’0’.
0
1
Set by the user to enable the CPU sleep state. CPU remains in Sleep mode until any interrupt is
pending.
0
1
0
1
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
No watchdog reset has occurred.
Watchdog reset has occurred.
Power on reset has not occurred and watchdog timer is enabled.
Is set after external reset or power on reset.
Normal operation.
Sleep.
M8C is free to execute code.
M8C is halted and is only cleared by POR, XRES, or WDR.
CPU_F register on page
WDRS
RC : 0
5
RC : 1
PORS
4
254. This bit is read only for GIES. Its use is discouraged, as the
RW : 0
Sleep
3
2
x,FFh
Register Definitions on
1
RW : 0
STOP
0
[+] Feedback