CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 198

IC MCU 32K FLASH 32UQFN

CY8CTMG200-32LQXI

Manufacturer Part Number
CY8CTMG200-32LQXI
Description
IC MCU 32K FLASH 32UQFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet

Specifications of CY8CTMG200-32LQXI

Program Memory Type
FLASH (32 kB)
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Applications
Touchscreen Controller
Core Processor
M8C
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Mounting Style
SMD/SMT
Program Memory Size
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2954

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EP0_CR
21.3.11
This register is an endpoint 0 control register.
For additional information, refer to the
Bit
7
6
5
4
3:0
198
Individual Register Names and Addresses:
EP0_CR : 0,36h
Access : POR
Bit Name
0,36h
Setup Received
IN Received
OUT Received
ACK’ed Transaction
Mode[3:0]
Name
EP0_CR
Endpoint 0 Control Register
Received
RC : 0
Setup
7
IN Received
RC : 0
6
Description
When set, this bit indicates a valid setup packet was received and ACK’ed.
When set, this bit indicates a valid IN packet was received.
When set, this bit indicates an OUT packet was received.
When set, this bit indicates a valid OUT packet has been received and ACK’ed.
The mode bits control how the USB SIE responds to traffic and how the USB SIE changes the mode
of that endpoint as a result of host packets to the endpoint.
Register Definitions on page 171
OUT Received
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
RC : 0
5
Transaction
ACK’ed
RC : 0
4
in the Full-Speed USB chapter.
3
2
Mode[3:0]
RW : 0
1
0,36h
0
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