CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 265

• Manufacturer Part Number: CY8CTMG200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2954

21.4.7
These registers endpoint control registers.
In the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 171
Bit
7
5
4
3:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
EP1_CR0 : 1,54h
EP5_CR0 : 1,58h
Access : POR
Bit Name
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
Name
in the Full-Speed USB chapter.
EPx_CR0
Endpoint Control Registers 0
RW : 0
Stall
7
EP2_CR0 : 1,55h
EP6_CR0 : 1,59h
6
Description
When this bit is set, the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls
an IN packet if the Mode bits are set to ACK-IN. This bit must be clear for all other modes.
When set, this bit causes an endpoint interrupt to be generated even when a transfer completes with
a NAK.
The ACK'ed transaction bit is set whenever the SIE engages in a transaction to the register's end-
point that completes with an ACK packet.
The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of
that endpoint as a result of host packets to the endpoint.
NAK_INT_EN
RW : 0
5
EP3_CR0 : 1,56h
EP7_CR0 : 1,5Ah
ACK’ed Tx
RC : 0
4
3
EP4_CR0 : 1,57h
EP7_CR0 : 1,5Bh
2
Mode[3:0]
RW : 0
Register Definitions on
1
1,54h
EPx_CR0
1,54h
0
265
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