CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 101

• Manufacturer Part Number: CY8CTMG200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2954

This chapter explains the Comparators for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated regis-
ters. For a complete table of the comparator registers, refer to the
erence of all registers in address order, refer to the
13.1
The CY8CTMG20x and CY8CTST200 PSoC devices contain two comparators designed to support capacitive sensing or
other general purpose uses.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
13. Comparators
AMuxBus
Reserved
Reserved
AMuxBus
Reserved
Reserved
(CS_CR3)
LPFilt[1:0]
VREF
RefLo
VREF
RefLo
RefHi
RefHi
P0[1]
P0[3]
(CMP_MUX)
P0[1]
P0[3]
(CMP_MUX)
INP0[1:0]
INN1[1:0]
(CMP_MUX)
(CMP_MUX)
INP1[1:0]
INN0[1:0]
Architectural Description
LPF
LPF_EN[1]
(CS_CR3)
LPF_EN[0]
(CS_CR3)
Enable, Range
Figure 13-1
(CMP_CR0)
Enable, Range
(CMP_CR0)
2
COMP1
2
COMP0
Comparator Analog System
shows a block diagram of the comparator system.
Figure 13-1. Comparators Block Diagram
CMP0 LUT
CMP1 LUT
Reg Write
Reg Write
Register Reference chapter on page
A
B
A
B
(CMP_LUT)
(CMP_LUT)
LUT1[3:0]
LUT0[3:0]
LUT
LUT
(CMP_CR1)
(CMP_CR1)
CRST1
CRST0
CMP1 LUT
CMP0 LUT
TrueTouch Register Summary on page
R
R
S
S
LATCH
LATCH
(CMP_CR1)
(CMP_CR1)
CDS1
CDS0
CPIN0 (CMP_CR1)
I/O Read
I/O Read
(CMP_CR1)
I/O Read
I/O Read
CPIN1
187.
CINT1
CINT0
(CMP_RDC)
CMP1
CMP0
(CMP_RDC)
(CMP_RDC)
(CMP_RDC)
CMP1D
CMP0L
CMP1O
CMP1L
CMP0O
CMP0D
CMP1
CMP0
84. For a quick ref-
To: Cap Sense Logic,
To: Pin Outputs
To: Cap Sense Logic,
To: Pin Outputs
To: Analog
Interrupt
101
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