AT94K05AL-25DQC Atmel, AT94K05AL-25DQC Datasheet - Page 8
AT94K05AL-25DQC
Manufacturer Part Number
AT94K05AL-25DQC
Description
IC FPSLIC 5K GATE 25MHZ 208PQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K05AL-25DQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
208-MQFP, 208-PQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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2.7
2.8
8
Cell Connections
The Cell
AT94KAL Series FPSLIC
In
neighbors. Section (b) of
buses (one per busing plane) and five vertical local buses (one per busing plane).
Figure 2-3.
Figure 2-4
muxes and pass gates are independent. All permutations of programmable muxes and pass
gates are legal. Vn is connected to the vertical local bus in plane n. Hn is connected to the hori-
zontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass
gates connected to Vn and Hn. Up to five simultaneous local/local turns are possible.
The logic cell can be configured in several “modes”. The logic cell flexibility makes the FPGA
architecture well suited to all digital design application areas, see
automatically optimizes designs to utilize the cell flexibility.
Figure 2-3
CELL
CELL
CELL
depicts the AT40K FPGA embedded core logic cell. Configuration bits for separate
section (a) depicts direct connections between an FPGA cell and its eight nearest
Cell Connections
(a) Cell-to-Cell Connections
Figure 2-3
Y
X
X
CELL
CELL
CELL
Y
Y
X
X
Y
shows the connections between a cell five horizontal local
CELL
CELL
CELL
Figure
(b) Cell-to-Bus Connections
2-5. The IDS layout tool
W
X
Y
Z
L
WXYZL
CELL
1138I–FPSLI–1/08
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