AT94K05AL-25DQC Atmel, AT94K05AL-25DQC Datasheet - Page 134

• Manufacturer Part Number: AT94K05AL-25DQC
• Description: IC FPSLIC 5K GATE 25MHZ 208PQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25DQC

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

134
AT94KAL Series FPSLIC
UART0 Control and Status Registers – UCSR0A
UART1 Control and Status Registers – UCSR1A
• Bit 7 - RXC0/RXC1: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift register to
UDRn. The bit is set regardless of any detected framing errors. When the RXCIEn bit in UCS-
RnB is set, the UART Receive Complete interrupt will be executed when RXCn is set (one).
RXCn is cleared by reading UDRn. When interrupt-driven data reception is used, the UART
Receive Complete Interrupt routine must read UDRn in order to clear RXCn, otherwise a new
interrupt will occur once the interrupt routine terminates.
• Bit 6 - TXC0/TXC1: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift regis-
ter has been shifted out and no new data has been written to UDRn. This flag is especially useful
in half-duplex communications interfaces, where a transmitting application must enter receive
mode and free the communications bus immediately after completing the transmission.
When the TXCIEn bit in UCSRnB is set, setting of TXCn causes the UART Transmit Complete
interrupt to be executed. TXCn is cleared by the hardware when executing the corresponding
interrupt handling vector. Alternatively, the TXCn bit is cleared (zero) by writing a logic 1 to the
bit.
• Bit 5 - UDRE0/UDRE1: UART Data Register Empty
This bit is set (one) when a character written to UDRn is transferred to the Transmit shift register.
Setting of this bit indicates that the transmitter is ready to receive a new character for
transmission.
When the UDRIEn bit in UCSRnB is set, the UART Transmit Complete interrupt will be executed
as long as UDREn is set and the global interrupt enable bit in SREG is set. UDREn is cleared by
writing UDRn. When interrupt-driven data transmittal is used, the UART Data Register Empty
Interrupt routine must write UDRn in order to clear UDREn, otherwise a new interrupt will occur
once the interrupt routine terminates.
UDREn is set (one) during reset to indicate that the transmitter is ready.
• Bit 4 - FE0/FE1: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming char-
acter is zero.
The FEn bit is cleared when the stop bit of received data is one.
• Bit 3 - OR0/OR1: OverRun
Bit
$0B ($2B)
Read/Write
Initial Value
Bit
$02 ($22)
Read/Write
Initial Value
7
RXC0
R
0
7
RXC1
R
0
6
TXC0
R/W
0
6
TXC1
R/W
0
5
UDRE0
R
1
5
UDRE1
R
1
4
FE0
R
0
4
FE1
R
0
3
OR0
R
0
3
OR1
R
0
2
-
R
0
2
-
R
0
1
U2X0
R/W
0
1
U2X1
R/W
0
0
MPCM0
R/W
0
0
MPCM1
R/W
0
1138I–FPSLI–1/08
UCSR0A
UCSR1A