AT94K05AL-25DQC Atmel, AT94K05AL-25DQC Datasheet - Page 115

• Manufacturer Part Number: AT94K05AL-25DQC
• Description: IC FPSLIC 5K GATE 25MHZ 208PQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25DQC

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.28.1.3
4.28.2
1138I–FPSLI–1/08
16-bit Multiplication
Example 3 – Multiply-accumulate Operation
The final example of 8-bit multiplication shows a multiply-accumulate operation. The general for-
mula can be written as:
Typical applications for the multiply-accumulate operation are FIR (Finite Impulse Response)
and IIR (Infinite Impulse Response) filters, PID regulators and FFT (Fast Fourier Transform). For
these applications the FMULS instruction is particularly useful. The main advantage of using the
FMULS instruction instead of the MULS instruction is that the 16-bit result of the FMULS opera-
tion always may be approximated to a (well-defined) 8-bit format, see
Numbers” on page
The new multiply instructions are specifically designed to improve 16-bit multiplication. This sec-
tion presents solutions for using the hardware multiplier to do multiplication with 16-bit operands.
Figure 4-37
with a 32-bit result (C = A • B). AH denotes the high byte and AL the low byte of the A operand.
CMH denotes the middle high byte and CML the middle low byte of the result C. Equal notations
are used for the remaining bytes.
The algorithm is basic for all multiplication. All of the partial 16-bit results are shifted and added
together. The sign extension is necessary for signed numbers only, but note that the carry prop-
agation must still be done for unsigned numbers.
Figure 4-37. 16-bit Multiplication, General Algorithm
c n ( )
in
ldi
muls r19,r18 ; r1:r0 = variable A * variable B
add
adc
=
r18,PINB ; Get the current pin value on port B
r19,b
r16,r0
r17,r1
a n ( )
schematically illustrates the general algorithm for multiplying two 16-bit numbers
×
b
+
118.
; r17:r16 = r18 * r19 + r17:r16
; Load constant b into r19
; r17:r16 += r1:r0
c n 1
(
–
)
AH AL
+
+
+
=
(sign
(sign
AH * BH
CH
ext)
ext)
(sign ext)
CMH
AL * BH
AH * BL
AT94KAL Series FPSLIC
X
BH BL
CML
AL * BL
CL
“Using Fractional
115