AT94K05AL-25DQC Atmel, AT94K05AL-25DQC Datasheet - Page 66

• Manufacturer Part Number: AT94K05AL-25DQC
• Description: IC FPSLIC 5K GATE 25MHZ 208PQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25DQC

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

66
AT94KAL Series FPSLIC
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the
interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by
software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero),
the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable
bit is set (one), and will be executed by order of priority.
The status register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt routine. This must be handled by software.
External Interrupt Mask/Flag Register – EIMF
• Bits 3..0 - INT3, 2, 1, 0: External Interrupt Request 3, 2, 1, 0 Enable
When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The external interrupts are always negative
edge triggered interrupts, see
• Bits 7..4 - INTF3, 2, 1, 0: External Interrupt 3, 2, 1, 0 Flags
When a falling edge is detected on the INT3, 2, 1, 0 pins, an interrupt request is triggered. The
corresponding interrupt flag, INTF3, 2, 1, 0 becomes set (one). If the I-bit in SREG and the cor-
responding interrupt enable bit, INT3, 2, 1, 0 in EIMF, are set (one), the MCU will jump to the
interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
is cleared by writing a logic 1 to it.
Timer/Counter Interrupt Mask Register – TIMSK
• Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
• Bit 6 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt is executed
if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
Bit
$3B ($5B)
Read/Write
Initial Value
Bit
$39 ($39)
Read/Write
Initial Value
7
INTF3
R/W
0
7
TOIE1
R/W
0
6
INTF2
R/W
0
6
OCIE1A
R/W
0
“Sleep Modes” on page
5
INTF1
R/W
0
5
OCIE1B
R/W
0
4
INTF0
R/W
0
4
TOIE2
R/W
0
3
INT3
R/W
0
3
TICIE1
R/W
0
69.
2
INT2
R/W
0
2
OCIE2
R/W
0
1
INT1
R/W
0
1
TOIE0
R/W
0
0
INT0
R/W
0
0
OCIE0
R/W
0
1138I–FPSLI–1/08
EIMF
TIMSK