AT94K05AL-25DQC Atmel, AT94K05AL-25DQC Datasheet - Page 52

• Manufacturer Part Number: AT94K05AL-25DQC
• Description: IC FPSLIC 5K GATE 25MHZ 208PQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25DQC

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Software Control of System Configuration
AT94KAL Series FPSLIC
Stack Pointer – SP
The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space
locations $3E ($5E) and $3D ($5D). Future versions of FPSLIC may support up to 64K Bytes of
memory; therefore, all 16 bits are used.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to
point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when an address is pushed onto the
Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when an address
is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The software control register will allow the software to manage select system level configuration
bits.
Software Control Register – SFTCR
• Bits 7..4 - Res: Reserved Bits
These bits are reserved in the AT94K and always read as zero.
• Bit 3 - FMXOR: Frame Mode XOR (Enable/Disable)
This bit is XORed with the System Control Register’s Enable Frame Interface bit. The behavior
when this bit is set to 1 is dependent on how the SCR was initialized. If the Enable Frame Inter-
face bit in the SCR is 0, the FMXOR bit enables the Frame Interface when set to 1. If the Enable
Frame Interface bit in the SCR is 1, the FMXOR bit disables the Frame Interface when set to 1.
During AVR reset, the FMXOR bit is cleared by the hardware.
• Bit 2 - WDTS: Software Watchdog Test Clock Select
When this bit is set to 1, the test clock signal is selected to replace the AVR internal oscillator
into the associated watchdog timer logic. During AVR reset, the WDTS bit is cleared by the
hardware.
• Bit 1 - DBG: Debug Mode
Bit
$3E ($5E)
$3D ($5D)
Read/Write
Initial Value
Bit
$3A ($5A)
Read/Write
Initial Value
15
SP15
SP7
7
R/W
R/W
0
0
7
-
R
0
14
SP14
SP6
6
R/W
R/W
0
0
6
-
R
0
13
SP13
SP5
5
R/W
R/W
0
0
5
-
R
0
R/W
4
-
R
0
12
SP12
SP4
4
R/W
0
0
11
SP11
SP3
3
R/W
R/W
0
0
3
FMXOR
R/W
0
2
WDTS
R/W
0
10
SP10
SP2
2
R/W
R/W
0
0
1
DBG
R/W
0
9
SP9
SP1
1
R/W
R/W
0
0
0
SRST
R/W
0
8
SP8
SP0
0
R/W
R/W
0
0
1138I–FPSLI–1/08
SFTCR
SPH
SPL