EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 49
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
October 2007
Region0
8 LRIO clock
Region1
8 LRIO clock
Region2
8 LRIO clock
Region3
8 LRIO clock
Table 2–15. Available Clocking Connections for Transceivers in 2SGX130G
Region
Global
Clock
v
v
v
v
Clock Resource
.
Other Transceiver Features
Other important features of the Stratix II GX transceivers are the power
down and reset capabilities, external voltage reference and bias circuitry,
and hot swapping.
Calibration Block
The Stratix II GX device uses the calibration block to calibrate the on-chip
termination for the PLLs and their associated output buffers and the
terminating resistors on the transceivers. The calibration block counters
the effects of process, voltage, and temperature (PVT). The calibration
block references a derived voltage across an external reference resistor to
calibrate the on-chip termination resistors on the Stratix II GX device. The
calibration block can be powered down. However, powering down the
calibration block during operations may yield transmit and receive data
errors.
Dynamic Reconfiguration
This feature allows you to dynamically reconfigure the PMA portion and
the channel parameters, such as data rate and functional mode, of the
Stratix II GX transceiver. The PMA reconfiguration allows you to quickly
optimize the settings for the transceiver’s PMA to achieve the intended
bit error rate (BER).
RCLK 20-27
RCLK 20-27
RCLK 12-19
RCLK 12-19
Regional
Clock
8 Clock I/O
Bank 13
v
8 Clock I/O
Bank 14
v
Stratix II GX Device Handbook, Volume 1
Transceiver
8 clock I/O
Bank 15
v
Stratix II GX Architecture
8 Clock I/O
Bank 16
v
v
2–41
8 Clock I/O
Bank 17
v
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