EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 12
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Transceivers
2–4
Stratix II GX Device Handbook, Volume 1
capable of built-in self test (BIST) generation and verification. The
ALT2GXB megafunction in the Quartus II software provides a
step-by-step menu selection to configure the transceiver.
Figure 2–1
channel. Stratix II GX transceivers provide PCS and PMA
implementations for all supported protocols. The PCS portion of the
transceiver consists of the word aligner, lane deskew FIFO buffer, rate
matcher FIFO buffer, 8B/10B encoder and decoder, byte serializer and
deserializer, byte ordering, and phase compensation FIFO buffers.
Each Stratix II GX transceiver channel is also capable of BIST generation
and verification in addition to various loopback modes. The PMA portion
of the transceiver consists of the serializer and deserializer, the CRU, and
the high-speed differential transceiver buffers that contain pre-emphasis,
programmable on-chip termination (OCT), programmable voltage
output differential (V
Transmitter Path
This section describes the data path through the Stratix II GX transmitter.
The Stratix II GX transmitter contains the following modules:
■
■
■
■
■
■
■
■
Transmitter PLLs
Each transceiver block has two transmitter PLLs which receive two
reference clocks to generate timing and the following clocks:
■
■
The serializer uses high-speed clocks to transmit data. The serializer is
also referred to as parallel in serial out (PISO). The high-speed clock is fed
to the local clock generation buffer. The local clock generation buffers
divide the high-speed clock on the transmitter to a desired frequency on
a per-channel basis.
clocks.
Transmitter PLLs
Access to one of two PLLs
Transmitter logic array interface
Transmitter phase compensation FIFO buffer
Byte serializer
8B/10B encoder
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
High-speed clock used by the serializer to transmit the high-speed
differential transmitter data
Low-speed clock to load the parallel transmitter data of the serializer
shows the block diagram for the Stratix II GX transceiver
Figure 2–3
OD
), and equalization.
is a block diagram of the transmitter
Altera Corporation
October 2007
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