EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 26
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Transceivers
Figure 2–16. Receiver PLL and CRU
2–18
Stratix II GX Device Handbook, Volume 1
rx_cruclk
rx_locktorefclk
rx_locktodata
rx_datain
÷1, 2, 4
÷N
The receiver PLLs and CRUs can support frequencies up to 6.375 Gbps.
The input clock frequency is limited to the full clock range of 50 to
622 MHz but only when using REFCLK0 or REFCLK1. An optional
RX_PLL_LOCKED port is available to indicate whether the PLL is locked
to the reference clock. The receiver PLL has a programmable loop
bandwidth which can be set to low, medium, or high. The Quartus II
software can statically set the loop bandwidth parameter.
All the parameters listed are programmable in the Quartus II software.
The receiver PLL has the following features:
■
■
■
■
■
■
■
÷2
Operates from 600 Mbps to 6.375 Gbps.
Uses a reference clock between 50 MHz and 622.08 MHz.
Programmable bandwidth settings: low, medium, and high.
Programmable rx_locktorefclk (forces the receiver PLL to lock
to the reference clock) and rx_locktodata (forces the receiver PLL
to lock to the data).
The voltage-controlled oscillator (VCO) operates at half rate and has
two modes. These modes are for low or high frequency operation
and provide optimized phase-noise performance.
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and
25. Not all settings are supported for any particular frequency.
Two lock indication signals are provided. They are found in PFD
mode (lock-to-reference clock), and PD (lock-to-data).
Clock Recovery Unit (CRU)
PFD
÷1, 4, 5, 8, 10, 16, 20, or 25
Up
Down
Up
rx_pll_locked
Down
÷m
CP+LF
rx_freqlocked
rx_rlv[ ]
High Speed RCVD_CLK
Low Speed RCVD_CLK
VCO
Altera Corporation
October 2007
÷1, 2, 4
÷L
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