EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 144
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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High-Speed Differential I/O with DPA Support
High-Speed
Differential I/O
with DPA
Support
2–136
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Non-
Stratix II GX
Table 2–37. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Device
The TDO output buffer meets V
The TDO output buffer meets V
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
Input buffer must be 3.3-V tolerant.
Input buffer must be 2.5-V tolerant.
Input buffer must be 1.8-V tolerant.
Table
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
Buffer Power
2–37:
TDI Input
Stratix II GX devices contain dedicated circuitry for supporting
differential standards at speeds up to 1 Gbps. The LVDS differential I/O
standards are supported in the Stratix II GX device. In addition, the
LVPECL I/O standard is supported on input and output clock pins on the
top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following
high-speed I/O interconnect standards and applications:
■
■
■
There are two dedicated high-speed PLLs in the EP2SGX30 device and
four dedicated high-speed PLLs in the EP2SGX60, EP2SGX90, and
EP2SGX130 devices to multiply reference clocks and drive high-speed
differential SERDES channels.
Tables 2–38
PLL can clock in each of the Stratix II GX devices. In
2–41
channels driven directly by the PLL. The second row below it shows the
maximum channels a Fast PLL can drive if cross bank channels are used
from the adjacent center Fast PLL. For example, in the 780-pin
FineLine BGA EP2SGX30 device, PLL 1 can drive a maximum of
V
C C I O
v
v
v
OH
OH
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
Parallel RapidIO standard
,
v
the first row for each transmitter or receiver provides the number of
(1),
(1),
(1),
(MIN) = 2.4 V.
(MIN) = 2.0 V.
= 3.3 V
(1)
(4)
(4)
(4)
through
Stratix II GX TDO V
V
C C I O
v
v
v
v
2–41
(2),
(2),
= 2.5 V
(2)
(2)
(5)
(5)
show the number of channels that each Fast
C C I O
V
C C I O
Voltage Level in I/O Bank 4
v
v
v
v
= 1.8 V V
(3)
(3)
(6)
Level shifter
Level shifter
Level shifter
C C I O
required
required
required
v
= 1.5 V V
Tables 2–38
Altera Corporation
October 2007
Level shifter
Level shifter
Level shifter
C C I O
required
required
required
through
v
= 1.2 V
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