EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 230
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Timing Model
4–60
Stratix II GX Device Handbook, Volume 1
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination for each I/O standard and with 0 pF (except for PCI
and PCI-X which use 10 pF) loading and the timing is specified up to the
output pin of the FPGA device. The Quartus II software calculates the
I/O timing for each I/O standard with a default baseline loading as
specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (t
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in
clock pin to output pin timing for Stratix II GX devices.
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
2.
Table 4–52. Stratix II GX Device Timing Model Status
t
t
Simulate the output driver of choice into the generalized test setup,
using values from
Record the time to V
CO
xz
EP2SGX130
/t
EP2SGX30
EP2SGX60
EP2SGX90
from clock pin to I/O pin = delay from clock pad to I/O output
Device
register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay
zx
output register + IOE output register clock-to-output delay +
delay from output register to output pin + I/O output delay +
output enable pin delay
from clock pin to I/O pin = delay from clock pad to I/O
Table
Table
MEAS
4–53. Use the following equations to calculate
4–53.
.
Preliminary
CO
) at worst-case process,
Altera Corporation
Final
v
v
v
v
June 2009
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