EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 294
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
LVPECL
DDIO Column Output I/O
DDIO Column Output I/O
Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Table 4–103. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and
-5 Devices
Maximum DCD (ps) for
Maximum DCD (ps) for
Table 4–102
Table 4–103
Standard
Standard
assumes the input clock has zero DCD.
assumes the input clock has zero DCD.
Note (1)
Note (1)
3.3/2.5V
3.3/2.5V
180
140
150
150
150
125
240
440
375
325
330
330
330
330
180
390
430
355
350
335
320
TTL/CMOS
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
Input IO Standard (No PLL in the Clock Path)
1.8/1.5V
260
270
270
270
240
360
180
1.8/1.5V
495
450
430
385
490
410
405
390
375
385
385
390
360
180
SSTL-2
2.5V
155
180
60
60
55
85
70
SSTL-2
2.5V
170
120
105
160
180
90
85
80
65
70
60
60
60
90
SSTL/HSTL
1.8/1.5V
155
180
70
60
60
55
85
SSTL/HSTL
1.8/1.5V
HSTL12
160
110
100
155
100
180
95
75
70
65
80
70
70
70
1.2V
155
180
70
60
60
55
85
Unit
ps
ps
ps
ps
ps
ps
ps
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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