EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 163
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
October 2007
Notes for
(1)
(2)
(3)
(4)
JTAG
Configuration
Table 3–4. Stratix II GX Configuration Features (Part 2 of 2)
Scheme
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Stratix II GX decompression
feature is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
Table
3–4:
Download cable
MAX II device or microprocessor and
flash device
Configuration Method
Device Security Using Configuration Bitstream Encryption
Stratix II and Stratix II GX FPGAs are the industry’s first FPGAs with the
ability to decrypt a configuration bitstream using the AES algorithm.
When using the design security feature, a 128-bit security key is stored in
the Stratix II GX FPGA. To successfully configure a Stratix II GX FPGA
that has the design security feature enabled, the device must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II GX device. This nonvolatile memory does
not require any external devices, such as a battery back up, for storage.
1
Device Configuration Data Decompression
Stratix II GX FPGAs support decompression of configuration data, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
(4)
An encrypted configuration file is the same size as a
non-encrypted configuration file. When using a serial
configuration scheme such as passive serial (PS) or active serial
(AS), configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme is used with the design security or decompression
feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security nor the
decompression feature enabled. For more information about
this feature, contact an Altera sales representative.
Design Security Decompression
Stratix II GX Device Handbook, Volume 1
Configuration & Testing
Remote System
Upgrade
3–7
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