EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 239
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
June 2009
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
SU
H
CO
CLR
PRE
CLKL
CLKH
L U T
A D D E R
SU
H
CO
Table 4–56. LE_FF Internal Timing Microparameters
Table 4–57. IOE Internal Timing Microparameters (Part 1 of 2)
Symbol
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table
LE register setup time
before clock
LE register hold time after
clock
LE register
clock-to-output delay
Minimum clear pulse
width
Minimum preset pulse
width
Minimum clock low time
Minimum clock high time
4–56:
IOE input and output
register setup time
before clock
IOE input and output
register hold time after
clock
IOE input and output
register clock-to-output
delay
Parameter
Parameter
Internal Timing Parameters
Refer to
Min
Tables 4–56
149
204
204
612
612
170
372
90
62
Grade
-3 Speed
Min
122
101
72
Grade
-3 Speed
(1)
Max
378
619
94
Max
(1)
169
through
Min
157
214
214
642
642
170
372
Grade
95
62
-3 Speed
Min
128
101
75
Grade
-3 Speed
4–61
(2)
Max
397
650
99
Max
(2)
Stratix II GX Device Handbook, Volume 1
177
for internal timing parameters.
-4 Speed Grade
Min
101
167
227
227
683
683
170
372
62
DC and Switching Characteristics
Min
136
101
80
-4 Speed
Grade
Max
105
422
691
Max
188
Min
121
200
273
273
820
820
170
372
-5 Speed
62
Min
163
101
96
Grade
-5 Speed
Grade
Max
127
507
829
Max
226
Unit
4–69
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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