EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 164
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Configuration
3–8
Stratix II GX Device Handbook, Volume 1
f
memory, and transmit this compressed bitstream to Stratix II GX FPGAs.
During configuration, the Stratix II GX FPGA decompresses the bitstream
in real time and programs its SRAM cells. Stratix II GX FPGAs support
decompression in the FPP (when using a MAX II device or
microprocessor and flash memory), AS, and PS configuration schemes.
Decompression is not supported in the PPA configuration scheme nor in
JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by system designers.
Stratix II GX devices can help effectively deal with these challenges with
their inherent re programmability and dedicated circuitry to perform
remote system updates. Remote system updates help deliver feature
enhancements and bug fixes without costly recalls, reducing time to
market, and extending product life.
Stratix II GX FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios processor or user logic)
implemented in the Stratix II GX device can download a new
configuration image from a remote location, store it in configuration
memory, and direct the dedicated remote system upgrade circuitry to
initiate a reconfiguration cycle. The dedicated circuitry performs error
detection during and after the configuration process, recovers from any
error condition by reverting back to a safe configuration image, and
provides error status information. This dedicated remote system upgrade
circuitry avoids system downtime and is the critical component for
successful remote system upgrades.
Remote system configuration is supported in the following Stratix II GX
configuration schemes: FPP, AS, PS, and PPA. Remote system
configuration can also be implemented in conjunction with Stratix II GX
features such as real-time decompression of configuration data and
design security using AES for secure and efficient field upgrades.
Refer to the
chapter in volume 2 of the Stratix II GX Device Handbook for more
information about remote configuration in Stratix II GX devices.
Configuring Stratix II GX FPGAs with JRunner
The JRunner™ software driver configures Altera FPGAs, including
Stratix II GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables
in JTAG mode. The programming input file supported is in Raw Binary
File (.rbf) format. JRunner also requires a Chain Description File (.cdf)
Remote System Upgrades with Stratix II & Stratix II GX Devices
Altera Corporation
October 2007
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