EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet
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EP2SGX60EF1152C4N
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EP2SGX60EF1152C4N Summary of contents
Page 1
... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. Altera Corporation Section I. Stratix II GX Device Data Sheet ® devices. They contain feature definitions of the ...
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... Stratix II GX Device Data Sheet Section I–2 Stratix II GX Device Handbook, Volume 1 Altera Corporation ...
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... This section lists the Stratix II GX device features. ■ Altera Corporation October 2007 ® family of devices is Altera’s third generation of FPGAs Main device features: TriMatrix memory consisting of three RAM block sizes to ● implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 550 MHz global clock networks with regional clock ● ...
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... Support for CDR-based serial protocols, including PCI Express, ● Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, CEI-6G, CPRI, Serial RapidIO, SONET/SDH Dynamic reconfiguration of transceiver channels to switch ● between multiple protocols and data rates Individual transmitter and receiver channel power-down ● ...
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... DSP blocks 16 PLLs 4 Maximum user I/O 361 pins Altera Corporation October 2007 8B/10B encoder and decoder perform 8-bit to 10-bit encoding ● and 10-bit to 8-bit decoding Phase compensation FIFO buffer performs clock domain ● translation between the transceiver block and the logic array Receiver FIFO resynchronizes the received data with the local ● ...
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... FineLine BGA BGA BGA Table 1–3 lists the Maximum User I/O Pin Count 1,152-Pin 1,508-Pin FineLine BGA FineLine BGA (35 mm) (40 mm) — — — — — — — — 534 — 558 — — 650 — 734 Altera Corporation October 2007 ...
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... Updated Table 1–1. ● Updated Table 1–2. February 2006, v1.1 ● Updated Table 1–1. October 2005 Added chapter to the Stratix II GX Device v1.0 Handbook. Altera Corporation October 2007 Dimension 780 Pins 1.00 2 841 ) 29 × 29 Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook shows the revision history for this chapter ...
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... Document Revision History 1–6 Stratix II GX Device Handbook, Volume 1 Altera Corporation October 2007 ...
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... Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from. Altera Corporation October 2007 2. Stratix II GX Architecture ® ...
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... Gbps double-width mode) SDI (HD, 3G) CPRI (614 Mbps, 1228 Mbps, 2456 Mbps) Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps) Serial Bandwidth (Full Duplex) 51 Gbps 51 Gbps 102 Gbps 102 Gbps 153 Gbps 153 Gbps 204 Gbps 255 Gbps Altera Corporation October 2007 ...
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... Designers can preset Stratix II GX transceiver functions using the Quartus differential output voltage (V Stratix II GX transceiver channel supports various loopback modes and is Altera Corporation October 2007 Stratix II GX Transceiver Block Logic Array Channel 1 Channel 0 Supporting Blocks (PLLs, State Machines, ...
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... Byte serializer 8B/10B encoder Serializer (parallel-to-serial converter) Transmitter differential output buffer High-speed clock used by the serializer to transmit the high-speed differential transmitter data Low-speed clock to load the parallel transmitter data of the serializer Figure 2– block diagram of the transmitter Altera Corporation October 2007 ...
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... The incoming reference clock can be selected from five inter-transceiver block lines IQ[4..0] or from the global clock line that is driven by an input pin. Altera Corporation October 2007 Note (1) TX Clock Transmitter Local ...
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... Data rate support Multiplication factor (W) Bandwidth Transmitter PLL 0 High-Speed Transmitter PLL0 Clock ÷ VCO L High-Speed Transmitter PLL Clock Transmitter PLL 1 ÷ L VCO High-Speed Transmitter PLL1 Clock Specifications 50 MHz to 622.08 MHz 600 Mbps to 6.375 Gbps 10, 16, 20, 25 Low, medium, or high Altera Corporation October 2007 ...
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... FPGA interface. Table 2–3. Transmitter Data with the Byte Serializer Enabled If the byte serializer is disabled, the FPGA transmit data is passed without data width conversion. Altera Corporation October 2007 Input Data Width 16 bits 20 bits ...
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... Note (1) Single-Width Mode Without Byte With Byte Serialization/ Serialization/ Deserialization Deserialization 0.6 to 2.5 0.6 to 3.125 Figure 2–5 for a Double-Width Mode Without Byte With Byte Serialization/ Serialization/ Deserialization Deserialization 5 6.375 diagrams the 10-bit Altera Corporation October 2007 ...
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... CTRL[1.. MSB Upon power on or reset, the 8B/10B encoder has a negative disparity which chooses the 10-bit code from the RD-column. However, the running disparity can be changed via the tx_forcedisp and tx_dispval ports. Altera Corporation October 2007 8B/10B Conversion MSB sent last Figure 2– ...
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... See IEEE 802.3 See IEEE 802.3 reserved code reserved code groups groups 1 Other value Description Dxx.y Normal data Idle in ||I|| K28.5 K28.5 Idle in ||T|| K28.4 Sequence K27.7 Start K29.7 Terminate K30.7 Error Reserved code groups K30.7 Invalid XGMII character Altera Corporation October 2007 ...
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... The Stratix II GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at rates up to 6.375 Gbps. The common mode voltage (V of the output driver is programmable. The following V available when the buffer is in 1.2- and 1.5-V PCML. ■ ■ Altera Corporation October 2007 is a diagram of the serializer. Note (1) 10 Low-speed ...
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... Stratix II GX Device Handbook, Volume 1 Stratix II GX Transceiver Architecture Overview Figure . CM Output Buffer Programmable Pre-Emphasis Programmable Output Driver 100 Ω 120 Ω 150 Ω External termination chapter in 2–8, is directly driven by the Programmable Output Termination Pins ) can be changed OD Altera Corporation October 2007 ...
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... ALT2GXB megafunction or dynamically through the dynamic reconfiguration controller. Figure 2–10. Pre-Emphasis Signaling Altera Corporation October 2007 – × single-ended voltage swing. The common HIGH LOW ...
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... V CM Programmable Output Driver Receiver differential input buffer Receiver PLL lock detector, signal detector, and run length checker Clock/data recovery (CRU) unit Deserializer Pattern detector Word aligner /V – 1) × 100, where MAX MIN is MIN 50, 60 Altera Corporation October 2007 ...
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... Figure 2–12. Receiver Input Buffer Input Pins Programmable Termination The programmable termination can be statically set in the Quartus II software. termination. The termination can be disabled if external termination is provided. Altera Corporation October 2007 Lane deskew Rate matcher 8B/10B decoder Byte deserializer Byte ordering Receiver phase compensation FIFO buffer ...
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... V CM 50, 60 Ω Receiver External Termination and Biasing V DD 50/60/75- Ω Termination Resistance C1 R1/ × {R2/( 2)} = 0.85/1 Receiver External Termination and Biasing Transmission Line Differential Input Buffer Figure 2–14 shows an example Stratix II GX Device R1 Receiver RXIP R2 RXIN Altera Corporation October 2007 ...
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... If the receive channel associated with a particular receiver PLL or CRU is not used, the receiver PLL and CRU are powered down for the channel. circuits. Altera Corporation October 2007 The Stratix II GX receivers also have adaptive equalization capability that adjusts the equalization levels to compensate for changing link characteristics ...
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... Programmable frequency multiplication 10, 16, 20, and 25. Not all settings are supported for any particular frequency. Two lock indication signals are provided. They are found in PFD mode (lock-to-reference clock), and PD (lock-to-data). ÷L CP+LF VCO ÷ rx_freqlocked rx_rlv[ ] High Speed RCVD_CLK Low Speed RCVD_CLK Altera Corporation October 2007 ...
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... Table 2–6. Receiver Lock Combinations If the rx_locktorefclk and rx_locktodata ports are not used, the default is auto mode. Deserializer (Serial-to-Parallel Converter) The deserializer converts a serial bitstream into 8, 10, 16 bits of parallel data. The deserializer receives the LSB first. the deserializer. Altera Corporation October 2007 rx_locktodata rx_locktorefclk ...
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... SONET/SDH should reverse the bit order of word align patterns programmed. 2–20 Stratix II GX Device Handbook, Volume 1 Note (1) High-speed serial clock Low-speed parallel clock Figure 2–17: This is a 10-bit deserializer. The deserializer can also convert 8, 16 bits of data Altera Corporation October 2007 ...
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... Once a pattern is detected and the data bus is aligned, the word boundary is locked. The two detection status signals (rx_syncstatus and rx_patterndetect) indicate that an alignment is complete. Figure 2–18 Figure 2–18. Word Aligner Altera Corporation October 2007 is a block diagram of the word aligner. datain Word ...
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... In all the SONET/SDH modes, you can configure the word aligner to either align to A1A2 or A1A1A2A2 patterns. Once the pattern is found, the word boundary is aligned and the word aligner asserts the rx_patterndetect signal for one clock cycle. 2–22 Stratix II GX Device Handbook, Volume 1 Handbook, volume 2. Altera Corporation October 2007 ...
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... For every rising edge of the rx_bitslip signal, the current word boundary is slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit slipping shifts a complete round of bus width, the word boundary is back to the original boundary. Altera Corporation October 2007 Table 2–7. ...
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... Figure 2–19. Before and After the Channel Aligner Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 2–24 Stratix II GX Device Handbook, Volume 1 shows misaligned channels before the channel aligner and Altera Corporation October 2007 ...
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... Matcher wrclock rdclock Standard Table 2–8: Refer to the Stratix II GX Transceiver User Guide Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture dataout Table 2–8 Note (1) PPM ± 100 ± 300 ± 100 ± 300 ® for the Altera -defined scheme. 2–25 ...
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... This 8B/10B decoder conforms to the IEEE 802.3 1998 edition standards. 2–26 Stratix II GX Device Handbook, Volume 1 (Figure 2–21) is part of the Stratix II GX transceiver Altera Corporation October 2007 ...
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... The 8B/10B decoder in double-width mode translates the 20-bit (2 × 10-bits) encoded code into the 16-bit (2 × 8-bits) equivalent data or control code. The 20-bit upper and lower symbols received must be from the supported Dx.y or Kx.y list with the proper disparity or error flags Altera Corporation October 2007 dataout[15..8] 8B/10B ...
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... FPGA interface and 2–28 Stratix II GX Device Handbook, Volume 1 shows how the 20-bit code is decoded to the 16-bit data + Cascaded 8B/10B Conversion Table 2–9). The FPGA interface has a limit of 250 MHz, so the byte Parallel Data Altera Corporation October 2007 a 0 LSB ...
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... FPGA boundary and cannot be bypassed. This FIFO buffer compensates for phase differences and clock tree timing skew between the receiver clock domain within the transceiver and the receiver FPGA clock after it has transferred to the FPGA. Altera Corporation October 2007 Deserialized Output Data Width to the Input Data Width (Bits) ...
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... Reverse serial loopback (pre-CDR) PCI Express PIPE reverse parallel loopback (available only in PIPE mode) 2–10. shows the BIST data output and verifier alignment pattern. Pattern Polynomial 8-Bit PRBS-7 ×7 + × ×10 + × Parallel Data Width 10-Bit 16-Bit 20-Bit v v Altera Corporation October 2007 ...
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... The data is looped back after the end of PCS and before the PMA. On the receive side, an internal BIST verifier checks for errors. This loopback enables you to verify the PCS block. Altera Corporation October 2007 shows the data path in serial loopback mode. ...
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... BIST PRBS Generator 8B/10B Encoder 20 Byte Rate 8B/10B De- Match Decoder serializer FIFO Analog Receiver and Transmitter Logic Serializer Parallel Loopback BIST PRBS Verify Clock De- Deskew Word Recovery serializer FIFO Aligner Unit Altera Corporation October 2007 ...
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... The signal at the output is not exactly what is received since the signal goes through the output buffer and the VOD is changed to the VOD setting level. The pre-emphasis settings have no effect. Altera Corporation October 2007 shows the data path in reverse serial loopback mode. ...
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... Analog Receiver and Transmitter Logic Serializer Reverse Serial Pre-CDR Loopback BIST PRBS Verify Clock De- Deskew Word Recovery serializer FIFO Aligner Unit Analog Receiver and Transmitter Logic Serializer BIST PRBS Verify Clock De- Deskew Word Recovery serializer FIFO Aligner Unit Altera Corporation October 2007 ...
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... Inter Quad (I/Q) lines to clock the PLLs in the other quads. Figure 2–29 global clock connections for the EP2SGX130 device. Altera Corporation October 2007 shows the inter-transceiver line connections as well as the Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture 2– ...
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... Transmitter REFCLK0 ÷2 To IQ3 Transmitter REFCLK1 PLL 1 ÷2 IQ[4..0] Global clk line From Global Clock Line (3) IQ[4..0] Transceiver Clock Generator Block 4 Receiver PLLs PLL 0 4 Receiver PLLs 4 Receiver PLLs PLL 0 4 Receiver PLLs PLL 0 4 Receiver PLLs Altera Corporation October 2007 ...
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... Figure 2–30. Stratix II GX Receiver PLL Recovered Clock to Global Clock Connection CLK[3..0] Notes to (1) (2) Altera Corporation October 2007 Notes (1), (2) CLK[15..12 GCLK[15..12] GCLK[3 ...
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... CLK# pins are clock pins and their associated number. These are pins for global and local clocks. RCLK# pins are regional clock pins. RCLK [27..24] Stratix II GX Transceiver Block RCLK [23..20] RCLK Stratix II GX [19..16] Transceiver Block RCLK [15..12] Altera Corporation October 2007 ...
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... LRIO resources available for Stratix II GX devices with different numbers of transceiver blocks. Tables 2–12 to the transceiver block. Table 2–12. Available Clocking Connections for Transceivers in 2SGX30D Region0 8 LRIO clock Region1 8 LRIO clock Altera Corporation October 2007 summarizes the possible clocking connections for the Destination Receiver PLL Global Clock ...
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... RCLK 20-27 v RCLK 20-27 v RCLK 12-19 RCLK 12-19 Regional Bank 13 Bank 14 Clock 8 Clock I/O 8 Clock I/O RCLK 20-27 v RCLK 20-27 RCLK 12-19 RCLK 12-19 Transceiver Bank 14 Bank 15 8 Clock I/O 8 Clock I Transceiver Bank 15 Bank 16 8 clock I/O 8 Clock I Altera Corporation October 2007 v ...
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... Stratix II GX transceiver. The PMA reconfiguration allows you to quickly optimize the settings for the transceiver’s PMA to achieve the intended bit error rate (BER). Altera Corporation October 2007 Bank 13 Bank 14 Clock ...
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... Stratix II GX transceiver blocks. These reset signals can be controlled from the FPGA or pins. 2–42 Stratix II GX Device Handbook, Volume 1 Pre-emphasis settings Equalizer and DC gain settings Voltage Output Differential (V OD Table 2–16 shows the connectivity between the reset ) settings volume 2, for more Altera Corporation October 2007 ...
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... An on-chip resistor generates a tracking current that tracks on-chip resistor variation. These currents are mirrored and distributed to the analog circuitry in each channel. f For more information, refer to the chapter in volume 1 of the Stratix II GX Handbook. Altera Corporation October 2007 ...
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... Multi-port single-protocol switching (for example, PCI Express, GIGE, XAUI switch, or SONET/SDH) shows Stratix II GX device resources. M4K RAM M-RAM Columns/Blocks Blocks Columns/Blocks 4/144 1 5/255 2 6/408 4 7/609 6 Figure 2–32 shows the DSP Block LAB LAB Rows Columns Altera Corporation October 2007 ...
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... The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 24 ALMs through fast local and direct link interconnects. Altera Corporation October 2007 Row Interconnects of Variable Speed & Length LAB Local Interconnect is Driven from Either Side by Columns & ...
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... Stratix II GX Device Handbook, Volume 1 shows the direct link connection. ALMs Direct link interconnect to right LAB Figure 2–34. Each LAB’s clock and Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output Altera Corporation October 2007 ...
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... Dedicated Row LAB Clocks 6 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation October 2007 shows the LAB control signal generation circuit. There are two unique clock signals per LAB. labclk0 labclk1 labclk2 labclkena0 labclkena1 ...
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... Stratix II GX Device Handbook, Volume 1 Figure 2–35 shows a high-level block Figure 2–36 carry_in reg_chain_in adder0 D adder1 D carry_out reg_chain_out shows a detailed To general or local routing To general or Q local routing reg0 To general or Q local routing reg1 To general or local routing Altera Corporation October 2007 ...
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... Figure 2–36. Stratix II GX ALM Details Altera Corporation October 2007 Stratix II GX Architecture Stratix II GX Device Handbook, Volume 1 2–49 ...
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... Stratix II GX Device Handbook, Volume 1 Figure Stratix II Performance and Logic Efficiency Analysis White Paper Normal mode Extended LUT mode Arithmetic mode Shared arithmetic mode Figure 2–35)—the eight data inputs from the LAB 2–36). For each set of output for Altera Corporation October 2007 ...
Page 59
... ALM to implement a single function six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions which have common inputs. Figure 2–37 Altera Corporation October 2007 for more information on the LAB-wide control shows the supported LUT combinations in normal mode. ...
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... LUT 5-Input combout1 LUT 6-Input combout0 LUT 6-Input combout0 LUT 6-Input combout1 LUT Altera Corporation October 2007 ...
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... Figure register1 and/or bypasses register1 and drives to the interconnect Altera Corporation October 2007 2–38. The shared inputs are dataa, datab, datac, and datad, Implementation in 1 ALM ...
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... The dataf1 input is available for register packing only if the six-input function is un-registered. Figure 2–40 Notes (1), (2) To general or local routing To general local routing reg0 To general local routing reg1 Figure 2–40 shows the occur naturally in designs. These Altera Corporation October 2007 ...
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... As shown in adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or un-registered versions of the adder outputs. Altera Corporation October 2007 combout0 D Q ...
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... Stratix II GX Device Handbook, Volume 1 carry_in adder0 4-Input LUT D Q reg0 4-Input LUT adder1 4-Input LUT D Q 4-Input reg1 LUT carry_out 2–42. The equation for this example is: To general or local routing To general or local routing To general or local routing To general or local routing Altera Corporation October 2007 ...
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... The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. Altera Corporation October 2007 Adder output is not used. ALM 1 X[0] Comb & ...
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... Stratix II GX Device Handbook, Volume 1 “MultiTrack Interconnect” on page 2–63 Figure 2–43 shows the ALM in shared arithmetic mode. for more information on Altera Corporation October 2007 ...
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... An example of a three-bit add operation utilizing the shared arithmetic mode is shown in sum (S[2..0]) and the partial carry (C[2..0]) is obtained using the LUTs, while the result (R[2..0]) is computed using the dedicated adders. Altera Corporation October 2007 shared_arith_in carry_in 4-Input ...
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... For enhanced fitting, a long shared arithmetic chain runs vertically 2–60 Stratix II GX Device Handbook, Volume 1 ALM Implementation ALM 1 3-Input X0 3-Input 3-Input 3-Input 2 1 ALM 2 13 3-Input X2 3-Input Y2 Z2 3-Input 3-Input shared_arith_in = '0' carry_in = '0' S0 LUT R0 C0 LUT S1 LUT R1 C1 LUT S2 LUT R2 C2 LUT '0' LUT R3 LUT Altera Corporation October 2007 ...
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... ALMs while saving local interconnect resources (see advantage of these resources to improve utilization and performance. See “MultiTrack Interconnect” on page 2–63 register chain interconnect. Altera Corporation October 2007 “MultiTrack Interconnect” on page 2–63 Figure 2–45). The Quartus II Compiler automatically takes ...
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... D reg1 reg_chain_out To general or local routing To general or Q local routing To general or Q local routing To general or local routing To general or local routing To general or Q local routing To general or Q local routing To general or local routing To Next ALM within the LAB Altera Corporation October 2007 ...
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... These row resources include: ■ ■ ■ Altera Corporation October 2007 Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left R24 row interconnects for high-speed access across the length of the device ...
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... LAB. 2–64 Stratix II GX Device Handbook, Volume 1 Notes (1), (2), (3) Adjacent LAB can C4 and C16 Drive onto Another Column Interconnects (1) LAB's R4 Interconnect LAB Primary LAB Neighbor LAB (2) Neighbor Figure 2–46 shows R4 R4 Interconnect Driving Right Altera Corporation October 2007 ...
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... The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. and register chain interconnects. Altera Corporation October 2007 Shared arithmetic chain interconnects in a LAB Carry chain interconnects in a LAB and from LAB to LAB Register chain interconnects in a LAB ...
Page 74
... Stratix II GX Device Handbook, Volume 1 Local Interconnect Routing Among ALMs in the LAB ALM 1 Register Chain Routing to Adjacent ALM's Register Input ALM 2 Local ALM 3 ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 Figure 2–48 shows the C4 interconnect connections Altera Corporation October 2007 ...
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... Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–48: (1) Each C4 interconnect can drive either up or down four rows. Altera Corporation October 2007 Note (1) Local Interconnect Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture C4 Interconnect Drives Local and R4 Interconnects ...
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... Local interconnect Direct link interconnect R4 interconnect R24 interconnect C4 interconnect C16 interconnect ALM M512 RAM block M4K RAM block M-RAM block DSP blocks 2–68 Stratix II GX Device Handbook, Volume 1 shows the Stratix II GX device’s routing scheme. Destination Altera Corporation October 2007 ...
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... Shift register ROM FIFO buffer Pack mode Byte enable Address clock enable Parity bits Mixed clock mode Memory initialization (.mif) Altera Corporation October 2007 Destination Table 2–19 shows the size and features of the different RAM M512 RAM Block M4K RAM Block (32 × ...
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... Simple dual-port RAM Single-port RAM FIFO ROM Shift register M-RAM Block (4K × 144 Bits Outputs unknown Output registers Unknown output 64K × 8 64K × 9 32K × 16 32K × 18 16K × 32 16K × × × × 128 4K × 144 Altera Corporation October 2007 ...
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... Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation October 2007 Figure 2–49 shows the M512 RAM block control signal 6 outclocken inclocken inclock outclock Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture wren outclr rden ...
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... Interconnect Region 2–72 Stratix II GX Device Handbook, Volume 1 36 dataout M4K RAM Block datain byte control enable signals clocks address 6 LAB Row Clocks Figure 2–50 R4 Interconnect Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB Altera Corporation October 2007 ...
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... A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Altera Corporation October 2007 True dual-port RAM Simple dual-port RAM ...
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... LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. RAM block to logic array interface. 2–74 Stratix II GX Device Handbook, Volume 1 6 clocken_b clock_b clock_a clocken_a renwe_b aclr_b renwe_a aclr_a Figure 2–52 shows the M4K Altera Corporation October 2007 ...
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... You cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. Altera Corporation October 2007 36 dataout M4K RAM ...
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... Stratix II GX Device Handbook, Volume 1 Figure clocken_a renwe_a aclr_b clocken_b aclr_a renwe_b Figure 2–54 and 2–56 show the interface between the M-RAM block and 2–53. Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_b Local Interconnect shows an example floorplan Altera Corporation October 2007 ...
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... Block M-RAM Block M4K M512 Blocks Blocks Note to Figure 2–54: (1) The device shown is an EP2SGX130 device. The number and position of M-RAM blocks varies in other devices. Altera Corporation October 2007 Stratix II GX Architecture Note (1) M-RAM Block M-RAM Block M-RAM Block DSP LABs ...
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... Only R24 and C16 interconnects cross the M-RAM block boundaries. 2–78 Stratix II GX Device Handbook, Volume 1 Note (1) Row Unit Interface Allows LAB Rows to Drive Port B Datain, Dataout, Address and Control Signals to and from M-RAM Block M-RAM Block Port LABs in Row M-RAM Boundary Altera Corporation October 2007 ...
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... Figure 2–56. M-RAM Row Unit Interface to Interconnect LAB Direct Link Interconnects Altera Corporation October 2007 C4 Interconnect R4 and R24 Interconnects Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture M-RAM Block dataout_a[ ] ...
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... R5 datain_b[71..57] byteena_b[7..6] TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX chapter in volume 2 of the Stratix II GX Device Handbook for more Output Signals dataout_a[11..0] dataout_a[23..12] dataout_a[35..24] dataout_a[47..36] dataout_a[59..48] dataout_a[71..60] dataout_b[11..0] dataout_b[23..12] dataout_b[35..24] dataout_b[47..36] dataout_b[59..48] dataout_b[71..60] Altera Corporation October 2007 ...
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... As indicated, the Stratix II GX DSP block can support one 36 × 36-bit multiplier in a single DSP block, and is true for any combination of signed, unsigned, or mixed sign multiplications. Altera Corporation October 2007 Table 2–21). Each DSP block can be configured to support up Eight 9 × 9-bit multipliers Four 18 × ...
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... Digital Signal Processing (DSP) Block Figures 2–57 Figure 2–57. DSP Blocks Arranged in Columns 4 LAB Rows 2–82 Stratix II GX Device Handbook, Volume 1 shows one of the columns with surrounding LAB rows. DSP Block Column DSP Block Altera Corporation October 2007 ...
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... Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications, and DSP blocks support Q1.15 format rounding and saturation. DSP block configured for 18 × 18-bit multiplier mode. Altera Corporation October 2007 shows the number of DSP blocks in each Stratix II GX device. Total 9 × 9 ...
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... CLRN Adder/ Subtractor/ Accumulator Optional Pipeline ENA Register Stage CLRN Optional Input Register Stage with Parallel Input or Shift Register Configuration Output Selection Multiplexer Summation Optional Output Register Stage Summation Stage for Adding Four Multipliers Together to MultiTrack Interconnect Altera Corporation October 2007 ...
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... ALMs. If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator stages are implemented in ALMs. Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks. Altera Corporation October 2007 Simple multiplier Multiply-accumulator Two-multipliers adder ...
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... Stratix II GX Device Handbook, Volume 1 and 2–60 show the DSP block interfaces to LAB rows. DSP Block OA[17..0] R4, C4 & Direct OB[17..0] Link Interconnects A1[17..0] B1[17..0] OC[17..0] OD[17..0] A2[17..0] B2[17..0] OE[17..0] OF[17..0] A3[17..0] B3[17..0] OG[17..0] OH[17..0] A4[17..0] B4[17..0] Altera Corporation October 2007 ...
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... LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in f Refer to the Stratix II GX Device Handbook for more information on DSP blocks. Altera Corporation October 2007 R4 Interconnect DSP Block Row Structure 16 ...
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... Data Inputs Data Outputs A1[17..0] OA[17..0] B1[17..0] OB[17..0] A2[17..0] OC[17..0] B2[17..0] OD[17..0] A3[17..0] OE[17..0] B3[17..0] OF[17..0] A4[17..0] OG[17..0] B4[17..0] OH[17..0] Altera Corporation October 2007 ...
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... These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally Altera Corporation October 2007 and 2–62. Internal logic and enhanced and fast PLL outputs Table 2– ...
Page 98
... The CLK pins symmetrically drive the RCLK networks in a particular quadrant, as shown in 2–90 Stratix II GX Device Handbook, Volume 1 Figure 2–61 CLK[15..12] Global Clock [15..0] Global Clock [15..0] CLK[7..4] Figure 2–62. shows the 12 dedicated CLK Altera Corporation October 2007 ...
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... Internal logic-array routing can also drive a dual-regional clock. Clock pins and enhanced PLL outputs on the top and bottom can drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on the left and right can drive vertical dual-regional clocks, as shown in Figure Altera Corporation October 2007 CLK[15..12 RCLK RCLK [31 ...
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... Stratix II GX Device Handbook, Volume 1 Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network CLK[3..0] PLLs Figure 2–64). Clocks Available to a Quadrant or Half-Quadrant Clock [23..0] CLK[15..12] CLK[7..4] Column I/O Cell IO_CLK[7..0] Lab Row Clock [5..0] Row I/O Cell IO_CLK[7..0] Altera Corporation October 2007 ...
Page 101
... Figure 2–65. EP2SGX30 Device I/O Clock Groups 8 24 Clocks in the Quadrant IO_CLKH[7..0] 8 IO_CLKG[7..0] 24 Clocks in the Quadrant 8 Altera Corporation October 2007 2–66 show the quadrant relationship to the I/O clock regions. IO_CLKA[7..0] IO_CLKB[7.. Clocks in the Quadrant 24 Clocks in the Quadrant 8 IO_CLKF[7 ...
Page 102
... Quadrant Quadrant 24 Clocks in the Quadrant Quadrant 8 8 IO_CLKK[7..0] IO_CLKJ[7..0] Clock source selection (dynamic selection for global clocks) Clock power-down (dynamic clock enable or disable) IO_CLKD[7..0] 8 I/O Clock Regions 8 IO_CLKE[7..0] 8 IO_CLKF[7..0] 8 IO_CLKG[7..0] 8 IO_CLKH[7..0] 8 IO_CLKI[7..0] Altera Corporation October 2007 ...
Page 103
... These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. (2) Only the CLKn pins on the top and bottom of the device feed to regional clock select. Altera Corporation October 2007 through 2–69 show the clock control block for the global ...
Page 104
... Stratix II GX Device Handbook, Volume 1 PLL Counter Outputs (c[5..0]) 6 Static Clock Select Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL_OUT Pin ( you can or .pof Altera Corporation October 2007 ...
Page 105
... I/O support. Enhanced and fast PLLs work together with the Stratix II GX high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. Altera Corporation October 2007 Stratix II GX Architecture Figures 2–67 through 2–69. ...
Page 106
... PLLs and 10 are not available in Stratix II GX devices. However, these PLLs are listed in the Stratix II GX PLL numbering scheme is consistent with Stratix and Stratix II devices. 2–98 Stratix II GX Device Handbook, Volume 1 Table 2–25 Notes (1), (2) Fast PLLs shows the PLLs available for Enhanced PLLs 10 ( Table 2–25 because Altera Corporation October 2007 ...
Page 107
... If the feedback input is used, you will lose one (or two (8) Every Stratix II GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL. Altera Corporation October 2007 shows the enhanced PLL and fast PLL features in Stratix II GX Enhanced PLL (1) m/(n × ...
Page 108
... Stratix II GX Device Handbook, Volume 1 shows a top-level diagram of the Stratix II GX device and PLL CLK[15..12 CLK[7..4] and 2–72 shows global and regional clocking from the fast Table 2–27. Altera Corporation October 2007 ...
Page 109
... The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. Altera Corporation October 2007 RCLK2 ...
Page 110
... Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part Left Side Global and Regional Clock Network Connectivity Clock pins CLK0p CLK1p CLK2p CLK3p 2–102 Stratix II GX Device Handbook, Volume 1 RCLK1 RCLK3 RCLK0 RCLK2 RCLK4 RCLK6 GCLK0 RCLK5 RCLK7 GCLK2 GCLK1 GCLK3 Altera Corporation October 2007 v ...
Page 111
... Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part Left Side Global and Regional Clock Network Connectivity Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 PLL 1 outputs PLL 2 outputs PLL 7 outputs Altera Corporation October 2007 ...
Page 112
... PLLs and Clock Networks Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part Left Side Global and Regional Clock Network Connectivity PLL 8 outputs 2–104 Stratix II GX Device Handbook, Volume Altera Corporation October 2007 ...
Page 113
... PLLs to the global and regional clock networks remains the same as shown. (2) If the design uses the feedback input, you will lose one (or two, if FBIN is differential) external clock output pin. Altera Corporation October 2007 shows the global and regional clocking from enhanced PLL ...
Page 114
... CLK14p v CLK15p CLK12n CLK13n CLK14n CLK15n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL5 outputs 2–106 Stratix II GX Device Handbook, Volume Table 2–28. The connections to Table 2–29 Altera Corporation October 2007 ...
Page 115
... Table 2–29. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs (Part Bottom Side Global and Regional Clock Network Connectivity Clock pins v CLK4p v CLK5p v CLK6p v CLK7p CLK4n CLK5n CLK6n CLK7n Drivers from internal logic GCLKDRV0 GCLKDRV1 Altera Corporation October 2007 ...
Page 116
... Table 2–29. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs (Part Bottom Side Global and Regional Clock Network Connectivity GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL 6 outputs Enhanced PLL 12 outputs 2–108 Stratix II GX Device Handbook, Volume Altera Corporation October 2007 ...
Page 117
... Stratix II GX devices contain up to four fast PLLs with high-speed serial interfacing ability. The fast PLLs offer high-speed outputs to manage the high-speed differential I/O interfaces. the fast PLL. Altera Corporation October 2007 shows a diagram of the enhanced PLL. Note (1) VCO Phase Selection ...
Page 118
... Programmable pull-up during configuration Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Post-Scale Counters ÷c0 8 ÷k ÷c1 4 ÷ ÷c3 8 chapter in volume 2 Altera Corporation October 2007 (2) diffioclk0 load_en0 (3) (3) load_en1 (2) diffioclk1 Global clocks Regional clocks to DPA block ...
Page 119
... Additionally, you can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. Altera Corporation October 2007 Open-drain outputs DQ and DQS I/O pins Double data rate (DDR) registers Figure 2– ...
Page 120
... IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. 2–112 Stratix II GX Device Handbook, Volume 1 OE Register Register CLK Q Input Register D Q Input Latch Input Register ENA Altera Corporation October 2007 ...
Page 121
... Altera Corporation October 2007 shows how a row I/O block connects to the logic array. C4 Interconnect ...
Page 122
... Stratix II GX Device Handbook, Volume 1 shows how a column I/O block connects to the logic array. Vertical I/O Block 32 LAB C4 & C16 Interconnects . Vertical I/O Block Contains up to Four IOEs IO_dataina[3..0] io_clk[7..0] IO_datainb[3..0] LAB Altera Corporation October 2007 ...
Page 123
... Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out. selection. Altera Corporation October 2007 “PLLs and Clock Networks” on for more information. illustrates the signal paths through the I/O block. ...
Page 124
... LAB, dedicated I/O clocks, and the column and row interconnects. shows the IOE in bidirectional configuration. 2–116 Stratix II GX Device Handbook, Volume 1 Note (1) ce_out clk_out clk_in ce_in sclr/spreset aclr/apreset oe Figure 2–81 Altera Corporation October 2007 ...
Page 125
... The optional PCI clamp is only available on column I/O pins. The Stratix II GX device IOE includes programmable delays that can be activated to ensure input IOE register-to-logic array register transfers, input pin-to-logic array register transfers, or output IOE register-to-pin transfers. Altera Corporation October 2007 Note (1) OE Register D ...
Page 126
... Programmable Delays Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin delay Delay to output enable pin CO Figure 2–82 shows an IOE configured for DDR input. Quartus II Logic Option Figure 2–83 Altera Corporation October 2007 ...
Page 127
... All input signals to the IOE can be inverted at the IOE. (2) This signal connection is only allowed on dedicated DQ function pins. (3) This signal is for dedicated DQS function pins only. (4) The optional PCI clamp is only available on column I/O pins. Altera Corporation October 2007 Stratix II GX Architecture Note (1) VCCIO To DQS Logic Block (3) ...
Page 128
... Figure 2–85 2–120 Stratix II GX Device Handbook, Volume Figure 2–84 shows the IOE configured for DDR output. shows the DDR output timing diagram. Altera Corporation October 2007 ...
Page 129
... All input signals to the IOE can be inverted at the IOE. (2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port. (3) The optional PCI clamp is only available on column I/O pins. Altera Corporation October 2007 Stratix II GX Architecture Notes (1), (2) ...
Page 130
... FineLine BGA EP2SGX130 1,508-pin FineLine BGA 2–122 Stratix II GX Device Handbook, Volume Table 2–31 shows the number of DQ and DQS buses that are Number of Number of ×4 Groups ×8/×9 Groups Number of Number of ×16/×18 ×32/×36 Groups Groups Altera Corporation October 2007 ...
Page 131
... You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom of the device. Altera Corporation October 2007 Figure 2–86 shows the phase-shift reference circuit Notes ...
Page 132
... I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the I Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. 2–124 Stratix II GX Device Handbook, Volume 1 chapter the standard Altera Corporation October 2007 ...
Page 133
... Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. Altera Corporation October 2007 shows the possible settings for the I/O standards with drive ...
Page 134
... LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL (on input and output clocks only) Differential 1.5-V HSTL class I and II Differential 1.8-V HSTL class I and II Differential SSTL-18 class I and II to prevent overdriving CCIO chapter in volume 1 of the CCIO CCIO Altera Corporation October 2007 ...
Page 135
... Voltage-referenced 1.5-V HSTL class I and II Voltage-referenced 1.8-V HSTL class I and II Voltage-referenced SSTL-18 class I and II Voltage-referenced Altera Corporation October 2007 Differential SSTL-2 class I and II 1.2-V HSTL class I and II 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-2 class I and II SSTL-18 class I and II ...
Page 136
... Type Voltage (V ) (V) REF 1.25 Selectable I/O Standards in Stratix II & Stratix II GX chapter in volume 2 of the Stratix II GX Device Handbook. Output Supply Board Termination Voltage (V ) (V) Voltage (V ) (V) CCIO TT 2.5 1.25 Figure 2–87. The two I/O banks Altera Corporation October 2007 ...
Page 137
... SSTL-2). Each I/O bank can support multiple standards with the same V input and output pins. Each bank can support one V example, when V 3.3-V PCI for inputs and outputs. Altera Corporation October 2007 Notes (1), (2) DQS ×8 DQS × ...
Page 138
... LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVTTL 1.5-V LVCMOS SSTL-2 class I and II SSTL-18 class I SSTL-18 class II 1.8-V HSTL class I 1.8-V HSTL class II 1.5-V HSTL class I 1.2-V HSTL Left Bank ( — — — Altera Corporation October 2007 ...
Page 139
... Stratix II GX Device Handbook. f For more information on differential on-chip termination, refer to the High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX Devices Altera Corporation October 2007 Top and Bottom Banks I/O Standard Support 3.3-V LVTTL 3.3-V LVCMOS 2 ...
Page 140
... Selectable I/O Standards in Stratix II & chapter in volume 2 of the Stratix II GX Device DC & Switching chapter in volume 1 of the Stratix II GX Device Handbook. Selectable I/O Standards in Stratix II & chapter in volume 2 of the Stratix II GX Device DC & Switching Characteristics chapter in values of S Altera Corporation October 2007 ...
Page 141
... These power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. The VCCPD pins also power configuration input pins and JTAG input pins. Altera Corporation October 2007 On-chip parallel termination with calibration is only supported for input pins. ...
Page 142
... CCIO supplies CC level of CCIO of the nCEO bank CCIO settings for the nCE input buffer of Altera Corporation October 2007 — — — — v ...
Page 143
... JTAG chain operation. Table 2–37. Supported TDO/TDI Voltage Combinations (Part TDI Input Device Buffer Power Stratix II GX Always V (3 Altera Corporation October 2007 contains board design recommendations to ensure that nCEO Stratix II GX nCEO V Voltage Level in I/O Bank 7 CCIO = 3 2 ...
Page 144
... Voltage Level in I/O Bank Level shifter Level shifter (3) required required v (3) Level shifter Level shifter required required v Level shifter Level shifter required required (6) Tables 2–38 through Altera Corporation October 2007 = 1.2 V ...
Page 145
... Transmitter/Receiver Total Channels Transmitter 780-pin FineLine BGA Transmitter 1,152-pin FineLine BGA Table 2–40. EP2SGX90 Device Differential Channels Package Transmitter/Receiver Transmitter 1,152-pin FineLine BGA Receiver Transmitter 1,508-pin FineLine BGA Receiver Altera Corporation October 2007 Note (1) Total Channels 29 31 Note (1) 29 Receiver 31 42 Receiver 42 Note (1) ...
Page 146
... Stratix II GX device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. of the Stratix II GX transmitter channel. 2–138 Stratix II GX Device Handbook, Volume 1 Note (1) Center Fast PLLs Total Channels PLL1 PLL2 Figure 2–88 shows the block diagram Corner Fast PLLs PLL7 PLL8 Altera Corporation October 2007 ...
Page 147
... You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel. In addition, you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array. Altera Corporation October 2007 10 10 ...
Page 148
... Stratix II GX receiver channel Data Realignment Circuitry Dedicated Receiver Synchronizer Interface diffioclk load_en chapter in volume 2 of the Stratix II GX Handbook. Data to R4, R24, C4, or direct link interconnect 10 Regional or global clock PLLs in Stratix II GX Altera Corporation October 2007 ...
Page 149
... Fast PLL 1 Fast PLL Note to Figure 2–90: (1) See Table 2–38 for the number of channels each device supports. Altera Corporation October 2007 Figure 2–90 shows the fast PLL and channel layout in EP2SGX60E, LVDS DPA Clock Clock Quadrant Quadrant LVDS DPA Clock Clock ...
Page 150
... Selectable I/O Standards in Stratix II & Stratix II GX Devices volume 2 of the Stratix II GX Handbook Stratix II GX Device Handbook, volume 2 Stratix II GX Transceiver Architecture Overview the Stratix II GX Handbook Note (1) Quadrant Quadrant chapter in Volume 2 of the chapter chapter in volume 2 of the chapter in chapter in volume 2 of Altera Corporation October 2007 ...
Page 151
... August 2007, v2.1 Added “Reverse Serial Pre-CDR Loopback” section. Updated Table 2–2. Added “Referenced Documents” section. Altera Corporation October 2007 Stratix II Performance and Logic Efficiency Analysis White Paper TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook shows the revision history for this chapter ...
Page 152
... Moved the “Stratix II GX Transceiver Clocking” section to after the “Receiver Path” section. 2–144 Stratix II GX Device Handbook, Volume 1 Changes Made Combined Chapter 02 “Stratix II GX Transceivers” and Chapter 03 “Stratix II GX Architecture” in the new Chapter 02 “Stratix II GX Architecture” Summary of Changes Altera Corporation October 2007 ...
Page 153
... Table 2–19 ● Table 2–29. Updated Figures 2–3, 2–9, 2–24, 2–25, 2–28, 2–29, 2–60, 2–62. Change 622 Mbps to 600 Mbps throughout the chapter. Altera Corporation October 2007 Changes Made Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture Summary of Changes 2–145 ...
Page 154
... Fast PLL Outputs” table. Updated notes to Tables 2–29 and 2–37. Updated notes to Figures 2–72, 2–73 and 2–74. Updated bulleted list in the “Advanced I/O Standard Support” section. 2–146 Stratix II GX Device Handbook, Volume 1 Changes Made table from the OD Summary of Changes Altera Corporation October 2007 ...
Page 155
... Updated Tables 3–19 through 3–22. ● Updated Tables 3–25 and 3–26. Updated “Fast PLL & Channel Layout” ● section. Altera Corporation October 2007 Changes Made Updated input frequency range in Table 2–4. Updated input frequency range in Table 2–4. Added 1,152-pin FineLine BGA package information for EP2SGX60 device in Table 3– ...
Page 156
... Table 2–42. Document Revision History (Part Date and Document Version Previous Chapter Updated Figure 3–56. 03 changes: December 2005 v1.1 Previous Chapter Added chapter to the Stratix II GX Device 03 changes: Handbook. October 2005 v1.0 2–148 Stratix II GX Device Handbook, Volume 1 Changes Made Summary of Changes Altera Corporation October 2007 ...
Page 157
... Stratix II GX devices also use the JTAG port to monitor the logic operation of the device with the SignalTap Stratix II GX devices support the JTAG instructions shown in 1 Altera Corporation October 2007 3. Configuration & Testing ® devices provide Joint Test Action Group (JTAG) ® ...
Page 158
... Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. (2) For more information on using the CONFIG_IO instruction, refer to the for Altera Devices White Paper. 3–2 Stratix II GX Device Handbook, Volume 1 Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins ...
Page 159
... Stratix II GX devices are configured at system power-up with data stored in an Altera configuration device or provided by an external controller (for example, a MAX Stratix II GX devices using the fast passive parallel (FPP), active serial ...
Page 160
... The PORSEL pin is a dedicated input used to select power-on reset (POR) delay times 100 ms during power up. When the PORSEL pin is connected to ground, the POR time is 100 ms. When the PORSEL pin is connected to V 3–4 Stratix II GX Device Handbook, Volume 1 3–6. , the POR time is 12 ms. CC Altera Corporation October 2007 ...
Page 161
... V/1.5 V, set V logic high and the V inputs to 1.8 V/1 For more information on multi-volt support, including information on using TDO and nCEO in multi-volt systems, refer to the Architecture Altera Corporation October 2007 and input pin selects which input buffer CCSEL is sampled during power-up ...
Page 162
... Remote system upgrades for remotely updating Stratix II GX designs summarizes which configuration features can be used in each Configuring Stratix II & Stratix II GX Devices Design Security Decompression v ( Table 3–4), chosen on the basis of the chapter in Remote System Upgrade Altera Corporation October 2007 ...
Page 163
... Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported. (4) The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the ByteBlasterMV parallel port download cable. ...
Page 164
... Stratix II GX devices. Configuring Stratix II GX FPGAs with JRunner The JRunner™ software driver configures Altera FPGAs, including Stratix II GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) 3– ...
Page 165
... For more information on the JRunner software driver, refer to the AN 414: An Embedded Solution for PLD JTAG Configuration files on the Altera web site (www.altera.com). Programming Serial Configuration Devices with SRunner A serial configuration device can be programmed in-system by an external microprocessor using SRunner. SRunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit into different embedded systems ...
Page 166
... Stratix II GX device is powered. Figure 3–1. External Temperature-Sensing Diode 3–10 Stratix II GX Device Handbook, Volume 1 PLLs in Stratix II & Stratix II GX Devices Figure 3–1. The temperature sensing diode is a Stratix II GX Device tempdiodep tempdioden chapter in volume 2 of Temperature-Sensing Device Altera Corporation October 2007 ...
Page 167
... Voltage (Across Diode) 0.65 0.60 0.55 0.50 0.45 0.40 –55 Altera Corporation October 2007 shows the specifications for bias voltage and current of the Parameter Minimum 80 8 0.3 Figure 3–2. –30 –5 20 Temperature (˚C) Stratix II GX Device Handbook, Volume 1 Configuration & ...
Page 168
... TSD. Switching I/O near the TSD pins can affect the temperature reading. Altera recommends you take temperature readings during periods of no activity in the device (for example, standby mode where no clocks are toggling in the device), such as when the nearby I/Os are state, and disable clock networks in the device ...
Page 169
... Added chapter to the Stratix II GX Device v1.0 Handbook. Altera Corporation October 2007 AN 357: Error Detection Using CRC in Altera FPGA Devices AN 414: An Embedded Solution for PLD JTAG Configuration AN 418 SRunner: An Embedded Solution for Serial Configuration Device Programming Configuring Stratix II & Stratix II GX Devices ...
Page 170
... Document Revision History 3–14 Stratix II GX Device Handbook, Volume 1 Altera Corporation October 2007 ...
Page 171
... Notes to Table 4–1: (1) See the Operating Requirements for Altera Devices Data Sheet (2) Conditions beyond those listed in operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. ...
Page 172
... Maximum Duty Cycles Condition (%) ( 4.0 V 100 Note (1) Minimum Maximum Unit (3) 1.15 1.25 (6) 3.135 3.465 (3.00) (3.60) (3) 2.375 2.625 (3) 1.71 1.89 (3) 1.425 1.575 (3) 1.15 1.25 (4) 3.135 3.465 –0.5 4 CCIO Altera Corporation June 2009 ...
Page 173
... CCH_B voltage Note to Table 4–4: (1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated. Altera Corporation June 2009 DC and Switching Characteristics Conditions For commercial use For industrial use Table 4–2 must rise monotonically from ground to V ...
Page 174
... Speed Commercial Speed Grade Grade Typ Max Min Typ - 622. 325 3 Altera Corporation June 2009 Units Ω Unit Max 622.08 MHz 325 MHz 3.3 V ...
Page 175
... Calibration block minimum power-down pulse width Time taken for one-time calibration PCI Express fixedclk Receiver clock Detect frequency Adaptive Equalization (AEQ) Altera Corporation June 2009 -4 Speed Commercial -3 Speed Commercial and Industrial Speed Speed Grade Min Typ Max Min -0 -0.3 - 0.2 - ...
Page 176
... Speed Commercial Speed Grade Grade Typ Max Min Typ - 50 2 100 - - 5000 600 - - 160 - 850±10% 1200±10% 100±15% 120±15% 150±15 Altera Corporation June 2009 Unit Max 50 MHz - ns 4250 Mbps 2 3 Ω Ω Ω - MHz - MHz - MHz ...
Page 177
... CDR LTR TIme (5), (9) CDR Minimum T1b (6), (9) LTD lock time (7), (9) Data lock time from rx_freqloc (8), (9) ked Programmable DC gain Transmitter Altera Corporation June 2009 -4 Speed Commercial -3 Speed Commercial and Industrial Speed Speed Grade Min Typ Max Min - ...
Page 178
... Grade Typ Max Min Typ - 5000 600 - 580±10% 680±10% 108±10% 125±10% 152±10 100 - - - 300 - - - 1562.5 500 - 1562.5 2500 1562 Altera Corporation June 2009 Unit Max 4250 Mbps mV mV Ω Ω Ω 100 ps 300 ps MHz 2125 MHz ...
Page 179
... DC-coupled LVDS links. ICM (12) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Make sure that input specifications are not violated during this period. Altera Corporation June 2009 -4 Speed Commercial -3 Speed Commercial and Industrial Speed ...
Page 180
... Invalid Data r x_dataout CDR LTR Time 4–10 Stratix II GX Device Handbook, Volume 1 shows the lock time parameters in manual mode, LTD = Lock to data LTR = Lock to reference clock LTR LTD lock time CDR Minimum T1b Figure 4–2 LTD Valid data Altera Corporation June 2009 ...
Page 181
... Figure 4–2. Lock Time Parameters for Automatic Mode CDR status r x_freqlocked r x_dataout Figures 4–3 output waveforms, respectively. Figure 4–3. Receiver Input Waveform Single-Ended Waveform V CM Differential Waveform Altera Corporation June 2009 LTR Invalid data Data lock time from rx_freqlocked and 4–4 show differential receiver input and transmitter V ID ...
Page 182
... V Note (1) V Setting (mV) OD 400 600 800 430 625 830 Positive Channel (p) Negative Channel (n) Ground p − Positive Channel (p) Negative Channel (n) Ground for data rates from OD 1000 1200 1400 1020 1200 1350 Altera Corporation June 2009 ...
Page 183
... Table 4–9. Typical Note to (1) Table 4–10. Typical Note to (1) Altera Corporation June 2009 Setting, TX Term = 120 Ω 1.5 V 240 480 Typical (mV) 260 510 Table 4–8: Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball. Setting, TX Term = 150 Ω ...
Page 184
... Note (1) V Setting (mV) OD 576 768 960 600 780 960 Note (1) Setting (mV) 720 960 730 960 Ω 329% 457% 156% 196% 237% 312% 97% 118% 141% 165% 68% 82% 95% 110% Altera Corporation June 2009 12 387% 200% 125% ...
Page 185
... Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball. Table 4–15. Typical Pre-Emphasis (First Post-Tap 1 Setting (mV) 300 32% 85% Altera Corporation June 2009 Note (1) (Part First Post Tap Pre-Emphasis Level 20% 26% 33% 41% Note (1) First Post Tap Pre-Emphasis Level 4 ...
Page 186
... First Post Tap Pre-Emphasis Level Ω TX Term = 100 86% 121% 170% 232% 54% 72% 95% 124% 36% 49% 64% 81% 25% 35% 44% 57 294% 386% 113% 133% 168% 196% 62% 75% 86% 96 333% 157% 195% 233% 307% 97% 117% 140% 161% 69% 82% 94% 108% Altera Corporation June 2009 12 242% 112% 12 373% 195% 127% ...
Page 187
... Note to Table 4–18: (1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball. Altera Corporation June 2009 Note (1) First Post Tap Pre-Emphasis Level Ω TX Term = 120 114% 166% 257% 355% 55% ...
Page 188
... Speed -3 Speed Commercial and Commercial Speed Industrial Speed Grade Grade Min Typ Max Min Typ ( (3) (Part 1 of 19) -5 Speed Commercial Speed Unit Grade Max Min Typ Max 0 0 0. 0 0.01 UI Altera Corporation June 2009 ...
Page 189
... Jitter frequency = Jitter tolerance at 1 MHz 2488.32 MBps Pattern = PRBS23 No Equalization DC Gain = 0 dB Jitter frequency = 10 MHz Pattern = PRBS23 No Equalization DC Gain = 0 dB Altera Corporation June 2009 DC and Switching Characteristics Notes (1), (2), -4 Speed -3 Speed Commercial and Commercial Speed Industrial Speed Grade Grade Min ...
Page 190
... Min Typ ( (18) > 0.37 > 0.37 > 0.31 > 0.31 (3) (Part 3 of 19) -5 Speed Commercial Speed Unit Grade Max Min Typ Max 0. 0. 0. 0. 0 0. 0.33 UI > 0.37 UI > 0.31 UI Altera Corporation June 2009 ...
Page 191
... Pattern = CJPAT V = 1200 Pre-emphasis XAUI Receiver Jitter Tolerance (9) Total jitter Pattern = CJPAT No Equalization DC Gain = 3 dB Deterministic jitter Pattern = CJPAT No Equalization DC Gain = 3 dB Altera Corporation June 2009 Notes -3 Speed Commercial and Commercial Speed Industrial Speed Grade Min Typ Max Min > 1.5 > 0.1 > ...
Page 192
... Speed Commercial Speed Unit Grade Max Min Typ Max > 8.5 UI > 0.1 UI > 0 0.25 UI > 0 0. 0.35 UI Altera Corporation June 2009 ...
Page 193
... Pattern = CJPAT Deterministic and Equalizer Setting = Random Jitter 0 for 1.25 Gbps Tolerance Equalizer Setting = (peak-to-peak) 6 for 2.5 Gbps Equalizer Setting = 6 for 3.125 Gbps Altera Corporation June 2009 DC and Switching Characteristics Notes (1), (2), -4 Speed -3 Speed Commercial and Commercial Speed Industrial Speed Grade ...
Page 194
... Speed Commercial and Commercial Speed Industrial Speed Grade Grade Min Typ Max Min Typ > 8.5 > 8.5 > 0.1 > 0.1 > 0.1 > 0.1 (3) (Part 7 of 19) -5 Speed Commercial Speed Unit Grade Max Min Typ Max > 8.5 UI > 0.1 UI > 0.1 UI Altera Corporation June 2009 ...
Page 195
... Gbps = REFCLK 187.5 MHz Pattern = CJPAT V = 1200 Pre-emphasis Total Jitter Data Rate = (peak-to-peak) 3.75 Gbps = REFCLK 187.5 MHz Pattern = CJPAT V = 1200 Pre-emphasis Altera Corporation June 2009 Notes -3 Speed Commercial and Commercial Speed Industrial Speed Grade Min Typ Max Min (12 0. 0.279 - (12) > ...
Page 196
... Stratix II GX Device Handbook, Volume 1 Notes -3 Speed Commercial and Commercial Speed Industrial Speed Grade Min Typ Max Min (13) > 0.37 > 0.65 > 8.5 (1), (2), (3) (Part 9 of 19) -4 Speed -5 Speed Commercial Speed Grade Grade Typ Max Min Typ Max - - - - - - Altera Corporation June 2009 Unit ...
Page 197
... BER = 10 (OIF) CEI Receiver Jitter Tolerance Deterministic Jitter Data Rate = Tolerance 6.375 Gbps (peak-to-peak) Pattern = PRBS31 Equalizer Setting = 15 DC Gain = 0 dB -12 BER = 10 Altera Corporation June 2009 Notes (1), (2), -4 Speed -3 Speed Commercial and Commercial Speed Industrial Speed Grade Min Typ Max Min > ...
Page 198
... Commercial Speed Industrial Speed Grade Min Typ Max Min > 0.988 > 5 > 0.05 Data > 0.05 (3) (Part 11 of 19) -4 Speed -5 Speed Commercial Speed Grade Grade Typ Max Min Typ Max N/A N/A N/A N/A N/A N/A N/A N/A Altera Corporation June 2009 Unit ...
Page 199
... Gbps = REFCLK 61.44 MHz for 614.4 Mbps and 1.2288 Gbps = REFCLK 122.88 MHz for 2.4576 Gbps Pattern = CJPAT Vod = 1400 mV No Pre-emphasis Altera Corporation June 2009 Notes (1), (2), -4 Speed -3 Speed Commercial and Commercial Speed Industrial Speed Grade Grade Min Typ ...
Page 200
... Stratix II GX Device Handbook, Volume 1 Notes (1), (2), -4 Speed -3 Speed Commercial and Commercial Speed Industrial Speed Grade Grade Min Typ Max Min Typ > 0.4 > 0.4 > 0.66 > 0.66 (3) (Part 13 of 19) -5 Speed Commercial Speed Unit Grade Max Min Typ Max N/A UI N/A UI Altera Corporation June 2009 ...