EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 86

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–14
Arria II Operational Mode Descriptions
Figure 4–7. 18-Bit Independent Multiplier Mode Shown for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
Independent Multiplier Modes
4–7:
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
This section describes the operation modes of Arria II devices.
In the independent input and output multiplier mode, the DSP block performs
individual multiplication operations for general-purpose multipliers.
9-Bit, 12-Bit, and 18-Bit Multiplier
You can configure each DSP block multiplier for 9-bit, 12-bit, or 18-bit multiplication.
A single DSP block can support up to eight individual 9 × 9 multipliers, six 12 × 12
multipliers, or up to four individual 18 × 18 multipliers. For operand widths up to
9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a
12 × 12 multiplier is implemented and for operand widths from 13 to 18 bits, an
18 × 18 multiplier is implemented. This is done by the Quartus II software by zero
padding the LSBs.
Figure
multiplier operation mode.
signals.
clock[3..0]
ena[3..0]
aclr[3..0]
4–7,
18
18
18
18
Figure
Half-DSP Block
4–8, and
output_saturate
output_round
Figure 4–9
Table 4–9 on page 4–30
signb
signa
show the DSP block in the independent
lists the DSP block dynamic
Chapter 4: DSP Blocks in Arria II Devices
36
36
overflow (1)
Arria II Operational Mode Descriptions
December 2010 Altera Corporation
result_1[ ]
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