EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 347
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Design Security
Table 9–26. Allowed Configuration Modes for Various Security Modes
December 2010 Altera Corporation
No key
Secure with volatile key
Board-level testing with
volatile key
Secure with non-volatile key
Board-level testing with
non-volatile key
Secure in tamper resistant
mode using volatile or
non-volatile key with tamper
protection set
Note to
(1) There is no impact to the configuration time required when compared with unencrypted configuration modes except when using FPP with AES
(and/or decompression), which requires DCLK that is ×4 the data rate.
Table
Security Mode
9–26:
1
Table 9–26
The design security feature is available in all configuration methods except JTAG.
Therefore, you can use the design security feature in FPP mode (when using an
external controller, such as a MAX II device or a microprocessor and flash memory),
or in AS, fast AS, and PS configuration schemes.
Unencrypted
Encrypted
Unencrypted
Encrypted
Unencrypted
Encrypted
Configuration
lists the configuration modes allowed in each of the security modes.
File
All configuration modes that do not engage the design security feature.
■
■
■
■
All configuration modes that do not engage the design security feature.
■
■
■
■
All configuration modes that do not engage the design security feature.
■
■
■
■
PS with AES (and/or with decompression)
FPP with AES (and/or with decompression)
Remote update AS or fast AS with AES (and/or with decompression)
AS or fast AS (and/or with decompression)
PS with AES (and/or with decompression)
FPP with AES (and/or with decompression)
Remote update AS or fast AS with AES (and/or with decompression)
AS or fast AS (and/or with decompression)
PS with AES (and/or with decompression)
FPP with AES (and/or with decompression)
Remote update AS or fast AS with AES (and/or with decompression)
AS or fast AS (and/or with decompression)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Allowed Configuration Modes
(Note 1)
9–67
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