EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 340
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9–60
Quartus II Software Support
Figure 9–28. Interface Signals between the ALTREMOTE_UPDATE Megafunction and the Nios II Processor
Arria II Device Handbook Volume 1: Device Interfaces and Integration
ALTREMOTE_UPDATE Megafunction
f
1
The user watchdog timer is disabled in factory configurations and during the
configuration cycle of the application configuration. It is enabled after the application
configuration enters user mode.
The Quartus II software provides the flexibility to include the remote system upgrade
interface between the Arria II device logic array and the dedicated circuitry, generates
configuration files for production, and allows remote programming of the system
configuration memory.
Use the ALTREMOTE_UPDATE megafunction option in the Quartus II software as
the interface between the remote system upgrade circuitry and the device logic array
interface. Using the megafunction block instead of creating your own logic saves
design time and offers more efficient logic synthesis and device implementation.
The ALTREMOTE_UPDATE megafunction provides a memory-like interface to the
remote system upgrade circuitry and handles the shift register read and write
protocol in the Arria II device logic. This implementation is suitable for designs that
implement the factory configuration functions using a Nios II processor or user logic
in the device.
Figure 9–28
megafunction and Nios II processor or user logic.
For more information about the ALTREMOTE_UPDATE megafunction and the
description of ports listed in
(ALTREMOTE_UPDATE) Megafunction User
Nios II Processor or
User Logic
shows the interface signals between the ALTREMOTE_UPDATE
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Figure
9–28, refer to the
read_param
write_param
param[2..0]
data_in[23..0]
reconfig
reset_timer
clock
reset
busy
data_out[23..0]
Guide.
ALTREMOTE_UPDATE
Remote Update Circuitry
December 2010 Altera Corporation
Quartus II Software Support
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