EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 303

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
AS and Fast AS Configuration (Serial Configuration Devices)
Table 9–11. Maximum Trace Length and Loading for the AS Configuration in Arria II Devices
December 2010 Altera Corporation
Arria II Device AS Pins
Guidelines for Connecting Serial Configuration Device to Arria II Devices
on an AS Interface
Estimating the AS Configuration Time
Programming Serial Configuration Devices
DATA[0]
DCLK
nCSO
ASDO
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and the Arria II devices must
follow the recommendations listed in
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Arria II device. This serial interface is clocked by the
Arria II DCLK output (generated from an internal oscillator or an option to select
CLKUSR as external clock source). Arria II devices support DCLK up to 40 MHz
(25 ns).
Therefore, you can estimate the minimum configuration time as the following:
RBF Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum
configuration time.
Enabling compression reduces the amount of configuration data that is transmitted to
the Arria II device, which also reduces configuration time. On average, compression
reduces configuration time, depending on your design.
Serial configuration devices are non-volatile, flash-memory-based devices. You can
program these devices in-system using an USB-Blaster™, EthernetBlaster,
EthernetBlaster II, or ByteBlaster™ II download cables. Alternatively, you can
program them using a microprocessor with the SRunner software driver.
You can perform in-system programming of serial configuration devices using the
conventional AS programming interface or JTAG interface solution.
Because serial configuration devices do not support the JTAG interface, the
conventional method to program them is using the AS programming interface. The
configuration data used to program serial configuration devices is downloaded using
programming hardware.
During in-system programming, the download cable disables device access to the AS
interface by driving the nCE pin high. Arria II devices are also held in reset mode by a
low level on nCONFIG. After programming is complete, the download cable releases
nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive GND and
logic high.
Maximum Board Trace Length from
the Arria II Device to the Serial
Configuration Device (Inches)
10
10
10
10
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table
9–11.
Maximum Board Load (pF)
15
30
30
30
9–23