EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 133
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–22. Phase Relationship Between PLL Clocks in No-Compensation Mode for Arria II Devices
Note to
(1) The PLL clock outputs can lag the PLL input clocks depending on routine delays.
Figure 5–23. Phase Relationship Between PLL Clocks in Normal Mode for Arria II Devices
Note to
(1) The external clock output can lead or lag the PLL internal clock signals.
December 2010 Altera Corporation
Figure
Figure
5–22:
5–23:
Dedicated PLL Clock Outputs (1)
External PLL Clock Outputs (1)
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software TimeQuest Timing Analyzer reports any phase
difference between the two. In normal mode, the delay introduced by the GCLK or
RCLK network is fully compensated.
phase relationship of the PLL clocks in normal mode.
Register Clock Port (1)
Register Clock Port
PLL Clock at the
PLL Clock at the
PLL Reference
PLL Reference
Clock at the
Clock at the
Input Pin
Input Pin
Phase Aligned
Phase Aligned
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure 5–23
shows an example waveform of the
5–29
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