EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 64
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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3–18
Figure 3–18. Shift-Register Memory Configuration
Arria II Device Handbook Volume 1: Device Interfaces and Integration
ROM Mode
FIFO Mode
f
1
w
W
W
W
W
×
m
Figure 3–18
All Arria II memory blocks support ROM mode. A .mif initializes the ROM contents
of these blocks. The address lines of the ROM are registered on M9K and M144K
blocks; however, they can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
All memory blocks support FIFO mode. MLABs are ideal for designs with many
small, shallow FIFO buffers. To implement FIFO buffers in your design, you can use
the FIFO MegaWizard Plug-In Manager in the Quartus II software. Both single- and
dual-clock (asynchronous) FIFOs are supported.
For more information about implementing FIFO buffers, refer to the
DCFIFO Megafunctions User
MLABs do not support mixed-width FIFO mode.
×
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
n Shift Register
m-Bit Shift Register
shows the memory block in shift-register mode.
Guide.
Chapter 3: Memory Blocks in Arria II Devices
W
W
W
W
December 2010 Altera Corporation
n Number of Taps
SCFIFO and
Memory Modes
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