EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 50

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–4
Figure 3–1. Byte Enable Functional Waveform for M9K and M144K
Arria II Device Handbook Volume 1: Device Interfaces and Integration
current data: q (asynch)
don't care: q (asynch)
contents at a0
contents at a1
contents at a2
Byte Enable Support
address
byteena
inclock
wren
data
1
All memory blocks support byte enables that mask the input data so that only specific
bytes of data are written. The unwritten bytes retain the previous written value. The
write enable (wren) signals, along with the byte enable (byteena) signals, control the
write operations of the RAM blocks.
The default value for the byte enable signals is high (enabled), in which case writing is
controlled only by the write enable signals. The byte enable registers have no clear
port. When using parity bits on the M9K and M144K blocks, the byte enable controls
all 9 bits (8 bits of data plus 1 parity bit). When using parity bits on the MLAB, the
byte-enable controls all 10 bits in the widest mode.
Byte enables operate in a one-hot fashion, with the LSB of the byteena signal
corresponding to the LSB of the data bus. For example, if you use a RAM block in ×18
mode, byteena = 01, data[8..0] is enabled and data[17..9] is disabled. Similarly, if
byteena = 11, both data[8..0] and data[17..9] are enabled. Byte enables are active
high.
You cannot use the byte enable feature when using the error correction coding (ECC)
feature on M144K blocks.
Figure 3–1
control the operations of the M9K and M144K memory blocks.
When a byte-enable bit is deasserted during a write cycle, the corresponding data byte
output can appear as either a “don’t care” value or the current data at that location.
The output value for the masked byte is controllable using the Quartus II software.
When a byte-enable bit is asserted during a write cycle, the corresponding data byte
output also depends on the setting chosen in the Quartus II software.
XXXX
XX
an
FFFF
doutn
doutn
shows how the write enable (wren) and byte enable (byteena) signals
FFFF
10
a0
FFFF
ABXX
ABFF
ABCD
01
a1
XXCD
FFCD
11
a2
ABCD
ABCD
ABFF
Chapter 3: Memory Blocks in Arria II Devices
a0
FFCD
ABFF
ABFF
December 2010 Altera Corporation
ABCD
a1
XXXX
XX
FFCD
FFCD
Memory Features
a2
ABCD
ABCD