EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 232

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–36
Figure 7–23. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Postamble Enable
dqsenable
DQS
In addition to the dedicated postamble register, Arria II GZ devices also have a
half-data rate (HDR) block inside the postamble enable circuitry. Use these registers if
the controller is running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit (shown in
Figure 7–26 on page
There is an AND gate after the postamble register outputs that is used to avoid
postamble glitches from a previous read burst on a non-consecutive read burst. This
scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency for
dqsenable de-assertion shown in
7–39).
Figure
7–23.
Chapter 7: External Memory Interfaces in Arria II Devices
Postamble
Arria II External Memory Interface Features
Postamble glitch
Preamble
December 2010 Altera Corporation
Delayed by
1/2T logic