EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 323

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Device Configuration Pins
Table 9–16. Dedicated Configuration Pins on the Arria II Device (Part 4 of 4)
December 2010 Altera Corporation
DATA0
DATA[7..1]
Notes to
(1) Arria II GZ devices do not support the 3.3 V I/O standard.
(2) To tri-state AS configuration pins in the user mode, turn on the Enable input tri-state on active configuration pins in user mode option from
Pin Name
the Device and Pin Options dialog box in the Configuration tab. This tri-states the DCLK, DATA0, nCSO, and ASDO pins.
(2)
Table
9–16:
User Mode
N/A
I/O
Configuration
configuration
PS, FPP, AS
schemes
Scheme
Parallel
(FPP)
Pin Type
Inputs
Input
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on the
DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor that is
always active.
For Arria II GX devices, DATA0 is a dedicated pin that is used
for both PS and AS configuration modes and is not available
as a user I/O pin after configuration.
For Arria II GZ devices, after PS or FPP configuration, DATA0
is available as a user I/O pin. The state of this pin depends on
the Dual-Purpose Pin settings.
Data inputs. Byte-wide configuration data is presented to the
target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tri-stated.
After FPP configuration, DATA[7..1] are available as user
I/O pins. The state of these pin depends on the
Dual-Purpose Pin settings.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Description
9–43