EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 487

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Transceiver Port List
Table 1–34. ALTGX Megafunction Reconfiguration Block Ports for Arria II Devices
Table 1–35. ALTGX Megafunction PIPE Interface Ports for Arria II Devices (Available only in PCIe functional mode)
December 2010 Altera Corporation
reconfig_clk
reconfig_fromgxb
reconfig_togxb[3:0]
pipe8b10binvpolarity
powerdn
tx_detectrxloopback
tx_forcedispcompliance
(Part 1 of 2)
Port Name
Port Name
f
Table 1–34
megafunction.
For more information about these ports, refer to
Reconfiguration in Arria II
Table 1–35
megafunction.
Input/Output
Input/Output
Output
Input
Input
Input
Input
Input
Input
lists the reconfiguration block port names and descriptions for the ALTGX
lists the PIPE interface port names and descriptions for the ALTGX
Dynamic reconfiguration clock. This clock is also used for offset cancellation
in all modes except PCIe mode.
The width of this signal is determined by the value you set in the What is the
number of channels controlled by the reconfig controller? option in the
Reconfiguration settings screen.
The width of this signal is fixed to four bits. It is independent of the value you
set in the What is the number of channels controlled by the reconfig
controller? option in the Reconfiguration settings screen.
PCIe polarity inversion control. Functionally equivalent to the RxPolarity
signal defined in PIPE specification revision 2.00. Available only in PCIe mode.
When asserted high, the polarity of every bit of the 10-bit input data to the
8B/10B decoder is inverted.
PCIe power state control. Functionally equivalent to the PowerDown[1:0]
signal defined in PIPE specification revision 2.00. The width of this signal is
2 bits and is encoded as follows:
■
■
■
■
Receiver detect or PCIe loopback control. Functionally equivalent to the
TxDetectRx/Loopback signal defined in PIPE specification revision 2.00.
When asserted high in the P1 power state with the tx_forceelecidle signal
asserted, the transmitter buffer begins the receiver detection operation. When
the receiver detect completion is indicated on the pipephydonestatus port,
this signal must be de-asserted.
When asserted high in the P0 power state with the tx_forceelecidle signal
de-asserted, the transceiver datapath is dynamically configured to support
parallel loopback, as described in
page
Forces the 8B/10B encoder to encode with a negative running disparity.
Functionally equivalent to the TxCompliance signal defined in PIPE
specification revision 2.00. Must be asserted high only when transmitting the
first byte of the PCI Express Compliance Pattern to force the 8B/10B encode
with a negative running disparity, as required by the PCIe protocol.
2'b00: P0—Normal Operation
2'b01: P0s—Low Recovery Time Latency, Low Power State
2'b10: P1—Longer Recovery Time Latency, Lower Power State
2'b11: P2—Lowest Power State
1–88.
Devices.
Description
Description
“PCIe (Reverse Parallel Loopback)” on
AN 558: Implementing Dynamic
Arria II Device Handbook Volume 2: Transceivers
1–101