EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 422

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–36
Figure 1–37. Example of Word Aligner Configured in Bit-Slip Mode
Arria II Device Handbook Volume 2: Transceivers
rx_patterndetect
rx_dataout[7:0]
rx_datain
rx_clkout
rx_bitslip
1
11110000
Bit-Slip Mode
In Basic, deterministic latency, and SDI functional modes, you can configure the word
aligner in bit-slip mode by selecting the Use manual bit slipping mode option in the
ALTGX MegaWizard Plug-In Manager.
Bit slip in the 10-bit wide word aligner allows 7-bit and 10-bit word alignment
patterns, whereas bit-slip in the 8-bit wide word aligner allows only a 16-bit word
alignment pattern. Other than this, the bit-slip operation is the same between the 8-bit
and 10-bit word aligner.
The rx_bitslip signal controls the word aligner operation in bit-slip mode. At every
rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the
received data stream, effectively shifting the word boundary by one bit. The
rx_patterndetect signal is driven high for one parallel clock cycle when the received
data after bit-slipping matches the 16-bit word alignment pattern programmed in the
ALTGX MegaWizard Plug-In Manager.
You can implement a bit-slip controller in the FPGA fabric that monitors either the
rx_dataout signal and/or the rx_patterndetect signal and controls the rx_bitslip
signal to achieve word alignment.
Figure 1–37
has the following events:
■
■
■
■
■
■
8'b11110000 is received back-to-back
16'b0000111100011110 is specified as the word alignment pattern
A rising edge on the rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB
position, forcing the rx_dataout to 8'b01111000
Another rising edge on the rx_bitslip signal at time n + 5 forces rx_dataout to
8'b00111100
Another rising edge on the rx_bitslip signal at time n + 9 forces rx_dataout to
8'b00011110
Another rising edge on the rx_bitslip signal at time n + 13 forces rx_dataout to
8'b00001111. At this instance, rx_dataout in cycles n + 12 and n + 13 are
8'b00011110 and 8'b00001111, respectively, which matches the specified 16-bit
alignment pattern 16'b0000111100011110. This results in the assertion of the
rx_patterndetect signal.
n
n + 1
shows an example of the word aligner configured in bit-slip mode, which
n + 2
01111000
n + 3
n + 4
n + 5
n + 6
11110000
00111100
n + 7
n + 8
Chapter 1: Transceiver Architecture in Arria II Devices
n + 9
n + 10
00011110
n + 11
n + 12
December 2010 Altera Corporation
n + 13
Receiver Channel Datapath
n + 14
00001111